Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Study of Bit Line Sense Amplifier for MRAM

MRAM의 Bit Line Sense Amplifier에 대한 연구

  • 홍승균 (중앙대학교 전자전기공학부) ;
  • 김인모 (중앙대학교 전자전기공학부) ;
  • 유혜승 (고려대학교 전자공학과) ;
  • 김수원 (고려대학교 전자공학과) ;
  • 송상훈 (중앙대학교 전자전기공학부)
  • Published : 2003.10.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposes a new BLSA(Bit Line Sense Amplifier) for MRAM. Current BLSA employs a latch-type circuit to amplify a signal from the selected memory cell. The proposed BLSA simplifies the circuit by amplifying the signal using cross-coupled PMOS transistors. It shows the same operation speedas the latch-type BLSA in simulation and occupies only 85% of the area taken by the latch-type BLSA.

본 논문에서는 MRAM에서 사용될 수 있는 새로운 Bit Line Sense Amplifier(BLSA)를 제안하였다. 기존의 BLSA는 기본적으로 Latch형 회로를 사용하여 Memory Cell로부터의 신호를 증폭한다. 제안된 BLSA는 Cross-coupled PMOS 트랜지스터를 사용하여 회로를 단순화하였으며. 기존 BLSA의 약 85%정도의 작은 면적을 차지하면서도 시뮬레이션상에서는 같은 동작 속도를 보이고 있다.

Keywords

References

  1. M. Durlam, P. Naji, M. DeHerrera, S. Tehrani, G. Kerszykowski, K. Kyler, 'Nonvolatile RAM based on Magnetic Tunnel Junction Elements', ISSCC Digest of Technical Paper, pp. 130-131, Feb. 2000
  2. S. S. P. Parkin, K. P. Roche, M. G. Samant, P. M. Roce, R. B. Beyers, and R. E. Scheuerlein, 'Exchange-biased magnetic tunnel junctions and appliction to nonvolatile magnetic random access memory', J. Appl. Phys., Vol. 85, No. 8, pp. 5828-5833, Apr. 1999 https://doi.org/10.1063/1.369932
  3. 유희준, 'DRAM의 설계', 홍릉과학출판사, 1996, pp. 37-52
  4. Eun-Jung Jang, Jung-Hwa Lee, Ji-hyun Kim, and Seung Lee, 'A Novel Sensing Circuit for 2T-2MTJ MRAM Applicable to High SpeedSynchronous Operation', JSTS, Vol. 2, No. 3, pp. 173-179, Sep. 2002
  5. Roy Scheuerlein, William Gallagher, Stuart Pakin, Alex Lee, Sam Ray, Ray Roberlazzi, and William Reohr, 'A 10ns Read and Write Non-Volatile Memory array Using a Magnetic Tunnel Junction and FET Switch in each Cell', ISSCC Digest of Technical Paper, pp. 128-129, Feb. 2000
  6. M. Durlam, P. Naji, A.Omair, M. DeHerrera, J. Calder, J. M. Slaughter, B. Engel, N. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. Ren, J. Molla, B. Feil, R. Willams, S. Tehrani, 'A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects', 2002 Symposium On VLSI Circuits Digest of Technical Papers, pp. 158-161, 2002
  7. S. Tehrani, J. M. Slaughter, M. DeHerrera, B. N. Engel, N. D. Rizzo, J. Salter, M. Durlam, R. W. Dave, J. Janesky, B. Butcher, K. Smith, G. Grynkewich, 'Magnetoresistive Random Access Memory Using Magnetic Tunnel Junctions', 703-714, May. 2003 https://doi.org/10.1109/JPROC.2003.811804
  8. M. Motoyoshi, K. Moriyama, H. Mori, C. Fukumoto, H. Itoh, H. Kano, K. Bessho, and H. Narisawa, 'High-Performance MRAM Technology with an Improved Magnetic Tunnel Junction Material', 2002 Symposium On VLSI Technology Digest of Technical Papers, pp. 212-213, 2002 https://doi.org/10.1109/VLSIT.2002.1015457
  9. M. I. Elmasry, 'Capacitance calculation in MOSFET VLSI,' IEEE Electron Device Lett., Vol. EDL-3, pp. 6-7, 1981
  10. IEEE Electron Device Lett. v.EDL-3 Capacitance calculation in MOSFET VLSI M.I.Elmasry