JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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3- Transistor Cell OTP ROM Array Using Standard CMOS Gate-Oxide Antifuse

  • Kim, Jin-Bong (Dept. of EECS, KAIST Also with MICROS Research Center) ;
  • Lee, Kwy-Ro (Dept. of EECS, KAIST Also with MICROS Research Center)
  • Published : 2003.12.01
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Abstract

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

Keywords

References

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