ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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A Viterbi Decoder with Efficient Memory Management

  • Lee, Chan-Ho (Department of Electronic Engineering, Soongsil University)
  • Received : 2003.01.15
  • Published : 2004.02.29
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Abstract

This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace-back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace-back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/($5{\times}$ constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace-back scheme. A Viterbi decoder complying with the IS-95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace-forward depth of 45.

Keywords

References

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