Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A 6-bit, 70MHz Modified Interpolation-2 Flash ADC with an Error Correction Circuit

오류 정정기능이 내장된 6-비트 70MHz 새로운 Interpolation-2 Flash ADC 설계

  • 박정주 (충북대학교 정보통신공학과) ;
  • 조경록 (충북대학교 정보통신공학과)
  • Published : 2004.05.01
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Abstract

In this thesis, a modified interpolation-2 6-bit 70MHz ADC is proposed minimizing chip area and power consumption, which includes an error correction circuit. The conventional flash ADC without interpolation comparators suffers from large chip area and more power consumption due to 2n resistors and 2n-1 comparators. Although the flash ADC with interpolation-4 comparators has small area, SNR, INL and DNL are degraded by comparison with the interpolation -2 comparator. We fabricated the proposed 6-bit ADC with interpolation-2 comparators using 0.18${\mu}{\textrm}{m}$ CMOS process. The ADC is composed of 32-resistors, 31 comparators, amplifiers, latches, error correction circuit, thermometer code detector and encoder As the results, power consumption is reduced to 40mW at 3.3V which is saving about 50% than a flash ADC without interpolation comparators, and area is reduced by 20%. SNR is increased by 75% in comparison with that of a flash ADC with interpolation-4 comparators.

본 논문에서는 새로운 interpolation-2 방식의 비교기 구조를 제안하여 칩 면적과 전력 소모를 줄이며 오류정정 회로를 내장하는 6-비트 70㎒ ADC를 설계하였다. Interpolation 비교기를 적용하지 않은 flash ADC의 경우 2n개의 저항과 2n -1개의 비교기가 사용되며 이는 저항의 수와 비교기의 수에 비례하여 많은 전력과 큰 면적을 필요로 하고 있다. 또한, interpolation-4 비교기를 적용한 flash ADC는 면적은 작으나 단조도, SNR, INL, DNL 특성이 떨어진다는 단점이 있었다. 본 논문에서 설계한 interpolation-2 방식의 ADC는 저항, 비교기, 앰프, 래치, 오류정정 회로, 온도계코드 디텍터와 인코더로 구성되며, 32개의 저항과 31개의 비교기를 사용하였다. 제안된 회로는 0.18㎛ CMOS 공정으로 제작되어 3.3V에서 40mW의 전력소모로 interpolation 비교기를 적용하지 않은 flash ADC에 비해 50% 개선되었으며, 칩 면적도 20% 감소되었다. 또한 노이즈에 강한 오류정정 회로가 사용되어 interpolation-4 비교기를 적용한 flash ADC 에 비해 SNR이 75% 개선된 결과를 얻었다.

Keywords

References

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