Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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New On-Chip RF BIST(Built-In Self Test) Scheme and Circuit Design for Defect Detection of RF Front End

RF Front End의 결함 검출을 위한 새로운 온 칩 RF BIST 구조 및 회로 설계

  • 류지열 (애리조나주립대학교 전기공학과) ;
  • 노석호 (안동대학교 전자공학과)
  • Published : 2004.04.01
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Abstract

This paper presents a novel defect detection method for one chip RF front end with fault detection circuits using input matching measurement. We present a BIST circuit using 40.25{\mu}m$ CMOS technology. We monitor the input transient voltage of the RF front end to differentiate faulty and fault-free RF front end. Catastrophic as well as parametric variation fault models are used to simulate the faulty response of the RF front end. This technique has several advantages with respect to the standard approach based on current test stimulus and frequency domain measurement. Because DUT and fault detection circuits are implemented in the same chip, this test technique only requires use of digital voltmeter (RMS meter) and RF voltage source generator for simpleand inexpensive testing.

본 논문에서는 입력 정합(input matching) BIST(Built-In Self-Test, 자체내부검사) 회로를 이용한 RF front end(고주파 전단부)의 새로운 결함 검사방법을 제안한다. 자체내부검사 회로를 가진 고주파 전단부는 1.8GHz LNA(Low Noise Amplifier, 저 잡음 증폭기)와 이중 대칭 구조의 Gilbert 셀 믹서로 구성되어 있으며, TSMC 40.25{\mu}m$ CMOS 기술을 이용하여 설계되었다. catastrophic 결함(거폭 결함) 및 parametric 변동 (미세 결함)을 가진 고주파 전단부와 결함을 갖지 않은 고주파 전단부를 판별하기 위해 고주파 전단부의 입력 전압특성을 조사하였다. 본 검사방법에서는 DUT(Device Under Test, 검사대상이 되는 소자)와 자체내부검사회로가 동일한 칩 상에 설계되어 있기 때문에 측정할 때 단지 디지털 전압계와 고주파 전압 발생기만 필요하며, 측정이 간단하고 비용이 저렴하다는 장점이 있다.

Keywords

References

  1. E. P. Vandamme, M. M. P. Schreurs, and C. van Dinther, 'Improved Three-Step De-Embedding Method to Accurately Account for the Influence of Pad Parasitics in Silicon On-Wafer RF Test-Structures', IEEE Tran. Electronic Devices, Vol. 48, No. 4, pp. 137-142, April 2001
  2. K. C. Craig, S. P. Case, R. E. Neese and C. D. DePriest, 'Current and Future Trusting in Automated RF and Microwave Testing', IEEE, pp. 183-186, 1994
  3. M. Soma, 'Challenges and Approaches in Mixed Signal RF Testing', IEEE, pp. 33-37, 1997
  4. W.A. Pleskacz, D. Kasprowicz, T. Oleszczak and W. Kuzmicz, 'CMOS Standard Cells Characterization for Defect Based Testing', IEEE International Symposium on DFT in VLSI Systems, 2001
  5. A.J. Bishop and A. Ivanov, 'On the Testability of CMOS Feedback Amplifiers', IEEE, pp. 65-73, 1994
  6. S. Yu, B.W. Jervis, K.R. Eckersall, I.M. Bell, A.G. Hall and G.E.Taylor, 'Neural Network Approach to fault Diagnosis in CMOS Opamp with Gate Oxide Short', Electronics Letters, Vol. 30, No. 9, pp. 695-696, April 1994 https://doi.org/10.1049/el:19940472
  7. A. Fathy et al, 'Design of Embedded Passive Component in LTCC-M Technology', IEEE MTT-S Digest, pp. 1281-1284, 1998
  8. D. Lupea et al, 'RF-BIST: Loopback Spectral Signature Analysis', IEEE Design, Automation and Test in Europe Conference and Exhibition, March 2003
  9. J. Dabrowski, BiST Model for IC RF-Tr-ansceiver Front-End, 2003 Proceedings of the 18th IEEE International Symposium on DEFECT and FAULT TOLERANCE in VLSI SYSTEMS, pp. 295-302, November 2003. [9]
  10. R. Voorakaranam, S. Cherubal and A. Chatterjee, A Signature Test Framework for Rapid Production Testing of RF Circuits, Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition, pp. 186-191, March 2003
  11. Z. H. Liu, 'Mixed-Signal Testing of Integrated Analog Circuits and Electronic Modules', PhD thesis, Ohio University, March 1999