The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
권호 표지
DOI QR코드

DOI QR Code

The Design of 10-bit 200MS/s CMOS Parallel Pipeline A/D Converter

10-비트 200MS/s CMOS 병렬 파이프라인 아날로그/디지털 변환기의 설계

  • 정강민 (성균관대학교 정보통신공학부)
  • Published : 2004.04.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

본 연구에서 매우 정밀한 샘플링을 필요로 하는 고해상도 비디오 응용면을 위하여 병렬 파이프라인 아날로그 디지털 변환기(ADC)를 설계하였다. 본 ADC의 구조는 4 채널의 10-비트 파이프라인 ADC를 병력 time-interleave로 구성한 구조로서 이 구조에서 채널 당 샘플링 속도의 4배인 200MS/s의 샘플링 속도를 얻을 수 있었다. 변환기에서 핵심이 되는 구성요소는 Sample and Hold 증폭기(SHA), 비교기와 연산증폭기이며 먼저 SHA를 전단에 설치하여 시스템 타이밍 요구를 완화시키고 고속변환과 고속 입력신호의 처리론 가능하게 하였다. ADC 내부 단들의 1-비트 DAC, 비교기 및 2-이득 증폭기는 한 개의 switched 캐패시터 회로로 통합하여 고속동작은 물론 저 전력소비가 가능한 특성을 갖도록 하였다. 본 연구의 연산증폭기는 2단 차동구조에 부저항소자를 사용하여 높은 DC 이득을 갖도록 보강하였다. 본 설계에서 각 단에 D-플립플롭(D-FF)을 사용한 지연회로를 구성하여 변환시 각 비트신호를 정렬시켜 타이밍 오차를 최소화하였다. 된 변환기는 3.3V 공급전압에서 280㎽의 전력소비를 갖고 DNL과 INL은 각각 +0.7/-0.6LSB, +0.9/-0.3LSB이다.

Keywords

References

  1. P. Scholtens and M.Vertregt, 'A 6-b 1.6-Gsample/s flash ADC in 0.18um CMOS using averaging termination,' IEEE JSSC, Vol.37, No.12, pp.1599-1609, 2002 https://doi.org/10.1109/JSSC.2002.804334
  2. Y. Li and E. Sinencio, 'A Wide Input Bandwidth 7-bit 300MSample/s Folding and Current-mode Interpolating ADC,' IEEE JSSC, Vol.38, No.8, pp.1405-1410, 2003 https://doi.org/10.1109/JSSC.2003.814429
  3. S. Yoo, J. Park, H. Yang, H. Bae, K. Moon, H. Park, S. Lee, J. Kim, 'A 10 b 150MS/s 123mW 0.18um CMOS popelined ADC,' Digest Tech, papers, ISSCC, pp.326-497, 2003
  4. D. Chang, U. Moon, 'A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique,' IEEE JSSC, Vol.38, Nol.8, pp.1401-1404, 2003 https://doi.org/10.1109/JSSC.2003.814427
  5. H. Chen, B. Song, K. Bacrania, 'A 14-b 20-MSample/s CMOS Popelined ADC,' IEEE JSSC, Vol.36, No.6, pp.997-1001, 2001 https://doi.org/10.1109/4.924862
  6. S. Mathur, M. Das, P.Tadeparthy, S.Ray, S. Mukherjee, B. Dinakaran, 'A 115 mW 12-bit 50MSps popelined ADC,' Symp, CVS, Vol.1, pp.913-916, 2002
  7. D. G. Nairn, 'A 10-bit, 3V, 100MS/s Pipelined ADC,' Proc. CICC, IEEE, pp.257-260, 2000 https://doi.org/10.1109/CICC.2000.852661
  8. S. Sonkusale,J . Van der Spiegel, K. Nagaraj, 'Background Digital Error Correction Technique for Pipeline ADCs,' IEEE Symp, ISCAS, Vol.1, pp.408-411, 2001 https://doi.org/10.1109/ISCAS.2001.921879
  9. L. Sumanen, M. Waltari, K. Halonen, 'A 10-bit 200 MS/s Parallel Pipeline A/D converter,' IEEE J. Solid State Circuits, Vol.36, No.7, July, 2001 https://doi.org/10.1109/4.933460
  10. S. Kiriaki, 'A 0.25mW sigma-delta modulator for voiceband applications,' in Symp, VLSI circuits Dig, Tech, Papers, pp.35-36, 1995 https://doi.org/10.1109/VLSIC.1995.520676
  11. W. Brigt, '8-b 75-MS/s 70-mW parallel pipelined ADC incorporating double sampling,' in ISSCC Dig, Tech, Papers, pp.146-147, Feb., 1998
  12. T. B. Cho and P. R. Gray, 'A 10-b 20Msample/s 35mW popeline A/D converter,' IEEE J. Solid-State Circuits, Vol.30, pp.166-172, 1995 https://doi.org/10.1109/4.364429
  13. M.de Wit, K.S.Tan and R. K. Hest, 'A 10-bit pipeline A/D converter with on chip precision trimmming,' IEEE J. Solid-State Circuit, Vol.28, pp.455-461, Apr., 1993 https://doi.org/10.1109/4.210028
  14. A, Karanicolas, H. LEE and K. Bacrania, 'A 15-b 1-M Sample/s digitally self-calibrated popeline ADC,' IEEE J. Solid-State Circuits, Vol.28, pp.1207-1215, Dec., 1993 https://doi.org/10.1109/4.261994
  15. D. Fu, K. Dyer, S. Lewis, P. Hurst, 'A Digital Back ground CalibrationTechnique for Time-Interleaved ADCs,' IEEE JSSC, Vol.33, No. 12, pp.1904-1911, 1998 https://doi.org/10.1109/4.735530
  16. V. Hakkarainen, L. Sumanen, M. Aho, M. Waltari, K. Halonen, 'A Self-Calibration Technique for Time Interleaved Pipeline ADCs,' Proc. ISCAS, Vol.1, pp.25-38, 2003
  17. Behzad Razavi, 'Principles of Data Conversion System Design,' IEEE PRESS, 1995
  18. Behzad Razavi, 'Principles of Data Conversion System Design,' IEEE PRESS, 1995
  19. David F. Hoeschele, Jr., 'Analog-to-Digital and Diital-to-Analog Conversion Technique,' JOHN WILEY & SONS, Vol.27, 1992
  20. Behzad Razavi, 'A 12-b5-Msample/s Two-step CMOS A/D Converter,' IEEE JSSC, Vol.27, 1992 https://doi.org/10.1109/4.173092