대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

휴대형기기에 적합한 내장형 3차원 그래픽 렌더링 처리기 설계

A design of The Embedded 3n Graphics Rendering Processor for Portable Devices

  • 발행 : 2004.11.01
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⟨ 이전 논문 다음 논문 ⟩

초록

기존의 3차원 그래픽 가속기는 전력소모 및 규모가 커서 휴대형 기기에는 적합하지 않다. 따라서 본 논문에서는 휴대형기기에 적합한 저전력 소규모의 3차원 렌더링 처리기를 제안한다. 소규모의 구현을 위하여 반복연산 및 고정소수점 연산을 사용하였다. 또 저전력의 고려를 위해 텍스쳐 유무에 따라 효율적으로 파이프라인을 관리하였고, 삼각형 셋업 및 에지워킹 단은 순차적으로, 3차원 영상 가속기의 성능을 좌우하는 스캔라인처리와 스팬처리 단은 병렬적으로 처리하게 설계하였다. 설계한 렌더링 처리기는 800*600의 해상도 지원과 32비트의 트루칼러를 지원하며 0.25㎛ ASIC공정에서는 50MHz로 동작하여 초당 47.88M 개의 픽셀과 33.25 프레임을 처리하며 텍스쳐 매핑을 포함 64만 게이트를 가지며 면적은 4.9827mm*4.9847mm 이이며 파워소모는 263.7mW이다.

This paper proposes 3D graphics accelerator, especially rendering unit, for portable devices. The existing 3D architecture is not suitable for portable devices because of its huge size. To reduce the size, we use iterative architecture and fixed-point calculation. In this paper, we suggest the format of fixed-point comparing with the result images, and some special technique to control. Finally, it is implemented with FPGA and 0.25um ASIC technology respectively. The ASIC chip can execute 47.88M pixels per second. The size of ASIC chip is 4.9287mm*4.9847mm and the power consumption is 263.7mW with 50MHz operation frequency.

키워드

참고문헌

  1. Hyun-Jea Woo, Jong-Chul Jeong, Moon-Key Lee.'The Design of efficient 3D graphics Rendering Architecture for mobile device 'Proc of KGS pp337-342, Jan,20
  2. Hyun-Jea Woo, Jong-Chul Jeong, Moon-Key Lee. 'An efficient, pipelined architecture for 3D graphics accelerator', Proc. of IEEK Summer Conference 2003, No.2, pp,1213-1216, July, 2003, Kor
  3. Hyun-Jea Woo, Jong-Chul Jeong, Moon-Key Lee.'The Design of 3D Graphics Rendering Processor for Portable Devices 'Proc. of 2003 SOC Design Conference ,NOV,20
  4. Hyun- Jae Woo, Jong-Chul Jeong, Moon-Key Lee, 'An Efficient Pipelined Architecture for 3D Graphics Accelerator', Proc. of IEEK Summer Conference 2002, No.2, pp.357-360, June, 2002, Korea
  5. Jong-Chul Jeong, Woo-Chan Park, Moon-Key Lee, Tack-Don Han, 'A New Technique to Solve Consistency Problem for 3D Parallel Rasterizer on a Single Chip', Proc. of Chunchon Multimedia Conference, pp.447-450, June, 2001, Chunchon, Korea
  6. Woong Jeong, Woo-Chan Park, Sung-Ho Kwak, Hoon-Mo Yang, Cheol-Ho Jeong, Tack-Don Han, and Moon-Key Lee, 'A New Pipelined Divider with a Small Lookup Table', Journal of IEEK, Vol. 40, No.9 pp.94-104, Sep. 2003-09-12
  7. Jong-Chul Jeong, Woong Jeong, Hyun-Jae Woo, Seung-Ho Kwak, Woo-Chan Park, Moon-Key Lee, Tak-don Han, 'A New Pipelined Divider with a Small Lookup Table', Proc. Of 2002 IEEE ASIA-PACIFIC Confemence on AISC, pp.33-36, August 6-8, 2002, Taipei, Taiw https://doi.org/10.1109/APASIC.2002.1031525
  8. D. Kirk, Unsolved Problems and Opportunities for High-Quality, High-Performance 3-D Graphics on a PC Platform, Proceedings of SIGGRAPH /Eurographics Workshop on Graphics Hardware, Keynote talk, Aug. 1998 https://doi.org/10.1145/285305.285306
  9. A. Kugler, The Setup for Triangle Rasterization, 11th Eurographics Workshop on Computer Graphics Hardware, pp. 1-10, August 1996
  10. Intel, Intel740 Graphics Accelerator Software Developer's Manual, Feb. 1998, http://support.intel.com/support/gaphics/intel740/
  11. J. McCormack, R. McNamara, C. Cianos,N. P. Jouppi, T. Dutton, J. Zurawski, L. Seiler, K Corell, Implementing Neon: A 256-bit Graphics Accelerator, IEEE Micro, pp. 58-69, April 1999 https://doi.org/10.1109/40.755468
  12. Mesa library, http://www.ssec.wisc.edu/~brianp/Mesa.html
  13. Quake 3, http://www.idsoftware.com/games/quake/quake3-aren
  14. M. Kameyarna, '3D Graphics LSI Core for Mobile Phone 'Z3D', Graphics Hardware 2003, pp.60-67
  15. Jon P. Ewins, Marcus D. Waller, Martin White and Paul F. Lister, 'Mip-Map Level Selection for Texture Mapping,' IEEE Transaction on Visualization and Computer Graphics, Vol.4, No.4, Oct.-Dec. 1998 https://doi.org/10.1109/2945.765326
  16. Compaq, 'Neon: A (Big) (Fast) Single-Chip 3D Workstation Graphics Accelerator,' July, 1999