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유한체 GF(2m)의 응용을 위한 새로운 나눗셈 회로

New Division Circuit for GF(2m) Applications

  • 김창훈 (대구대학교 컴퓨터공학과) ;
  • 이남곤 (대구대학교 정보통신공학과) ;
  • 권순학 (성균관대학교 수학과) ;
  • 홍춘표 (대구대학교 정보통신공학부)
  • 발행 : 2005.06.01

초록

본 논문에서는 유한체 $GF(2^m)$의 응용을 위한 새로운 비트-시리얼 나눗셈 회로를 제안한다. 제안된 나눗셈 회로는 수정된 바이너리 최대 공약수 알고리즘에 기반하며, 2m-1 클락 사이클 비율로 나눗셈 결과를 출력한다. 본 연구에서 제안된 회로는 기존의 비트-시리얼 나눗셈 회로에 비해 속도에서 $43\%$, 칩 면적에서 $20\%$의 성능 개선을 보인다. 또한 제안된 회로는 기약다항식의 선택에 있어 어떠한 제약 조건도 두지 않을 뿐 아니라 매우 규칙적이고 모듈화 하기 쉽기 때문에 필드 크기 m에 대해 높은 유연성 및 확장성을 제공한다. 따라서 본 논문에서 제안된 나눗셈 회로는 저면적을 요구하는 $GF(2^m)$의 응용에 매우 적합하다.

In this paper, we propose a new division circuit for $GF(2^m)$ applications. The proposed division circuit is based on a modified the binary GCD algorithm and produce division results at a rate of one per 2m-1 clock cycles. Analysis shows that the proposed circuit gives $47\%$ and $20\%$ improvements in terms of speed and hardware respectively. In addition, since the proposed circuit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Thus, the proposed divider. is well suited to low-area $GF(2^m)$ applications.

키워드

참고문헌

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피인용 문헌

  1. Design of FPGA Hardware Accelerator for Information Security System vol.18, pp.2, 2013, https://doi.org/10.9723/jksiis.2013.18.2.001