Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지

A Design of 10 bit Current Output Type Digital-to-Analog Converter

10-비트 전류출력형 디지털-아날로그 변환기의 설계

  • 권기협 (금오공과대학교 전자공학과) ;
  • 김태민 (구미1대학 정보통신과) ;
  • 신건순 (금오공과대학교 전자공학부)
  • Published : 2005.08.01
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Abstract

This paper describes a 3.3 V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method. Most of Dfh converters with hiか speed current drive are an architecture choosing current switch cell, column, row decoding method but this decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. The designed D/A converter with an active chip area of $0.953\;mm^2$ is fabricated by using a 0.35um process. The simulation data shows that the rise/fall time, settling time, and INL/DNL are 1.92/2.1 ns, 12.71 ns, and a less than ${\pm}2.3/{\pm}58$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3 V is about 224 mW.

본 논문은 상위 7비트와 하위 3비트의 segmented 전류원 구조로서 최적화 된 binary-thermal decoding 방식을 이용한 3.3v 10비트 CMOS D/A 변환기를 제안한다. segmeted 전류원 구조와 최적화 된 binary-thermal decoding 방식을 D/A 변환기가 지니므로 가질 수 있는 장점은 디코딩 논리회로의 복잡성을 단순화함으로 칩면적을 줄일 수 있다. 제안된 변환기는 0.35um CMOS n-well 표준공정을 이용하여 제작되었으며, 유효 칩면적은 $0.953mm^2$ 이다. 설계된 칩의 상승/하강시간, 정작시간 및 INL/DNL은 각각 1.92/2.1 ns, 12.71 ns, ${\pm}2.3/{\pm}0.58$ LSB로 나타났다. 또한 설계된 D/A 변환기는 3.3V의 공급전원에서는 224mW의 전력소모가 측정되었다.

Keywords

References

  1. T.-Y. Wu, C.-T. Jih, J. -C. Chen, and C.-Y. Wu, 'A Iow glitch 10-bit 75-MHz CMOS video D/A converter' IEEE J. Solid-State Circuits, vol. 30, no. 1, pp. 68-72, Jan. 1995 https://doi.org/10.1109/4.350191
  2. S.Y. Chin and C. -Y. Wu, 'A 10-b 125-MHz CMOS digital-to analog converter(DAC) with threshold-voltage compensated current sources' IEEE J. Solid-State Circuits, vol. 29, no. 11, pp. 1374-1380, Nov. 1994 https://doi.org/10.1109/4.328639
  3. Yasuyuki Nakamura, et al., 'A 10-b 70-Ms/s CMOS D/A converter' IEEE J. Solid-Sate Circuits, vol. 26, no. 4, pp. 637-642, Apr. 1991 https://doi.org/10.1109/4.75066
  4. K.-H.Ryu and D.-S. Yoon, 'A 3.3-V 65-MHz 12 bit CMOS digital to analog converter' Proceedings of ITC-CSCC '98, July 13-15, pp. 1439-1442. 1998
  5. T. Miki et al., 'An 80-MHz 8-bit CMOS D/A converter,' IEEE J. Solid-State Circuits, vol. SC-21, pp. 983-988, Dec. 1986
  6. 김 욱, '고속 고해상도 디지털-아날록 변환기의 설계에 관한 연구,' 서울 대학교 박사학위 논문. 1994
  7. Marcel J. M. Pelgrom, Aad C. J. Duinmaijer, and Anton P. G. Welbers, 'Matching properties of MOS transistors,' IEEE J. Solid-State Circuits, vol. 24, No. 5, pp. 1433-1439, Oct. 1989 https://doi.org/10.1109/JSSC.1989.572629
  8. Marcel J. M. Pelgrom, 'A 10-b 50-MHz CMOS D/A converter with 75-${\Omega}$ buffer' IEEE J. Solid-State Circuits, vol. SC-25, pp. 1374-1352, Dec. 1990
  9. Neil H. E. Weste and Karnran Eshraghian, Principles of CMOS VLSI Design, 2nd ed., Addition Wesley pub.co., New York, 1993
  10. David A. Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons. Inc, 1997
  11. J. M. Fourier and P. Senn, 'A 130-MHz 8-bCMOS video DAC for HDTV applications' IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 1073-1077, July. 1991 https://doi.org/10.1109/4.92028
  12. C. H. Lin and K. Huh, 'A 10-b 500-M Sample/s CMOS DAC in 0.6 $mm^2$' IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998 https://doi.org/10.1109/4.735535
  13. 김지현, 권영복, 윤광섭, '2단 전류셀 매트릭스 구조를 지닌 저전압 고속 8비트 CMOS D/A 변환기' 전자공학회지, vol. 35C, no. 4, pp. 50-59, 1998