Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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SMC: An Seed Merging Compression for Test Data

시드 병합을 통한 테스트 데이터의 압축방법

  • Lee Min-joo (Department of Electrical Electronic School, Yonsei University) ;
  • Jun Sung-hun (Department of Electrical Electronic School, Yonsei University) ;
  • Kim Yong-joon (Department of Electrical Electronic School, Yonsei University) ;
  • Kang Sumg-ho (Department of Electrical Electronic School, Yonsei University)
  • 이민주 (연세대학교 전기전자 공학부) ;
  • 전성훈 (연세대학교 전기전자 공학부) ;
  • 김용준 (연세대학교 전기전자 공학부) ;
  • 강성호 (연세대학교 전기전자 공학부)
  • Published : 2005.09.01
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Abstract

As the size of circuits becomes larger, the test method needs more test data volume and larger test application time. In order to reduce test data volume and test application time, a new test data compression/decompression method is proposed. The proposed method is based on an XOR network uses don't-care-bits to improve compression ratio during seed vectors generation. After seed vectors are produced seed vectors can be merged using two prefix codes. It only requires 1 clock time for reusing merged seed vectors, so test application time can be reduced tremendously. Experimental results on large ISCAS '89 benchmark circuits prove the efficiency of the proposed method.

회로가 커짐에 따라 테스트 데이터양이 증가하고, 테스트 적용시간이 길어지고 있다. 따라서 테스트 데이터양과 테스트 적용시간을 줄이기 위해서, 테스트 데이터의 압축/복원을 위한 새로운 방법을 제안하고자 한다. 제안하는 방법은 시드 벡터를 생성할 때, 압축률을 높이기 위해 무상관비트를 사용하는 XOR 트리에 기반을 두고 있다. 시드 벡터가 생성이 되면, 2비트 길이를 가진 코드를 사용하여 시드를 병합한다. 이렇게 병합된 시드는 1 클럭 시간동안에 재사용될 수가 있어, 테스트 데이터 적용시간을 크게 감소시킬 수 있다 제안하는 방법의 효율성은 ISCAS '89 벤치 회로에 대한 실험 결과로 알 수 있다.

Keywords

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