대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

3D 그래픽 Geometry Engine을 위한 부동소수점 연산기의 설계

Design of a Floating Point Unit for 3D Graphics Geometry Engine

  • 김명환 (서경대학교 컴퓨터공학과) ;
  • 오민석 (서경대학교 컴퓨터공학과) ;
  • 이광엽 (서경대학교 컴퓨터공학과) ;
  • 김원종 (한국전자통신연구원 SoC설계연구부) ;
  • 조한진 (한국전자통신연구원 SoC설계연구부)
  • 발행 : 2005.10.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 실시간 3D 가속을 효과적으로 하기 위해 기하학 처리 과정에 적합한 부동 소수점 연산기를 설계하였다. 설계한 부동 소수점 연산기는 IEEE-754 단정도 형식을 지원하도록 하여 기하학 처리에 적합하게 하였고 설계한 부동 소수점 연산기는 Xilinx-Vertex2에서 부동소수점 덧셈/곱셈기는 100 MHz, 부동소수점 NR 역수 계산기는 120 MHz, 부동 소수점 멱승기는 200 MHz, 부동 소수점 역 제곱근 연산기는 120 MHz의 동작 주파수를 각각 확인 하였다. 또한 설계된 부동소수점 연산기를 이용해 실제 기하학 프로세서를 구현하여 실제 3B 데이터 처리를 확인하였다.

In this paper, we designed floating point units to accelate real-time 3D Graphics for Geometry processing. Designed floating point units support IEEE-754 single precision format and we confirmed 100 MHz performance of floating point add/mul unit, 120 MHz performance of floating point NR inverse division unit, 200 MHz performance of floating point power unit, 120 MHz performance of floating point inverse square root unit at Xilinx-vertex2. Also, using floating point units, designed Geometry processor and confirmed 3D Graphics data processing.

키워드

참고문헌

  1. David H. Eberly, '3D Game Engine Design,' Morgan Kaufmann, May, 2001
  2. L. Garber, 'The wild world of 3D graphics chips,' IEEE Computer, Vol. 33, no. 9, pp. 12-16, Sep. 2000 https://doi.org/10.1109/MC.2000.868692
  3. Udo Flohr, '3-D for Everyone,' Byte, pp.76-88, Oct. 1996
  4. Foley, VanDam, Feiner, Hughes, 'Computer Graphics Principle and Practice,' Addison & Wesley, June 1996
  5. Tomas Akenine-Moller, Eric Haines, 'Real-Time Rendering,' AK Peters, Dec 2002
  6. J. G. Torborg, 'A Parallel Processor Architecture for Graphics Arithmetic Operations,' Proceeding of SIGGRAPH '87, pp.197-204, 1987 https://doi.org/10.1145/37401.37426
  7. Behrooz Parhami, 'Computer Arithmetic Algorithms and Hardware Design,' Oxford University Press, pp.128-211, 2000
  8. Jeong, Woo Kyeong 'A SIMD-DSPIFPU for High-Performance Embedded Microprocessors' Master's Theis, 2002
  9. Jong-Chul Jeong, Woo-Chan Park, Woong Jeong, Tack-Don Han, Moon-Key Lee ' A Cost-Effective Pipelined Divider with a Small Lookup Table' IEEE Transaction, pp489-495, 2004 https://doi.org/10.1109/TC.2004.1268407
  10. Hyun-Chul Shin, Jin-Aeon Lee, Lee-Sup Kim, 'A Hardware Cost Minimized Fast Phong Shader,' IEEE Transaction, pp297-304, 2001 https://doi.org/10.1109/92.924048
  11. Hyun-Chul Shin, 'A Hardware Implementation of fast Phong Shading using Taylor series approximation', Master Thesis, KAIST, Dec, 1997
  12. http://www.ssec.wisc.edu/brianpj Mesa.html
  13. Michael J, Schulte, KeFlt E, 'High-Speed Inverse Square Roots,' 14th IEEE Symposium, pp124-131, 1999 https://doi.org/10.1109/ARITH.1999.762837
  14. R. W. Stewart, R. Chapman, and T. Durrani, 'The Square Root in Signal Processing,' in Proceedings of Real-Time Signal Processing, pp.89-100, 1989
  15. Cheol-Ho Jeong, 'Design of an Effective Control and Execution Method for Geometry Engines and Rasterizers within Embedded 3D Graphics Accelerators,' Phd Thesis, Yonsei University, Dec, 2003
  16. F. Arakawa, O. Nishii, K Uchiyama, and N. Nakayama, 'SH4 RISe multimedia microprocessor,' IEEE Micro, Vol. 18, no. 2, pp.26-34, April 1998 https://doi.org/10.1109/40.671400
  17. Ju-ho Sohn, 'Design and Optimization of Geometry Acceleration for Portable 3D Graphics,' Master Thesis, KAIST, Dec, 2002
  18. Masatoshi Kameyama, Y oshiyuki Kato, Hitoshi Fujimoto, Hiroyasu Negishi, Yukio Kodama, Y oshitsugu Inoue, Hiroyuki Kawai, '3D graphics LSI core for mobile phone Z3D,' Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware, pp.60-67, 2003