Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A Low Jitter and Fast Locking Phase-Lock Loop with Adaptive Bandwidth Controller

  • Song Youn-Gui (Pukyong National University) ;
  • Choi Young-Shig (Dept. of Electronics and Telecommunication Engineering, Pukyong National University)
  • Published : 2005.03.01
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Abstract

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

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References

  1. Joonsuk Lee, and Beomsup Kim, 'A low-noise fast lock phase-locked loop with adaptive bandwidth con ntrol,' IEEE J, Solid-State Circuits, vol. 35, Aug. 2000, pp.1137-1145 https://doi.org/10.1109/4.859502
  2. M. Mizuno et al., 'A 0.18 ${\mu}m$ CMOS hot-stand by phase-locked loop using a noise immune adaptive gain voltage-controlled oscillator,' ISSCC Dig. Tech. Papers, Feb. 1995, pp. 268-269 https://doi.org/10.1109/ISSCC.1995.535551
  3. G. Roh, Y. lee, and B. Kim, 'An optimum phase-acq uisition technique for charge-pump phase-locked loops,' IEEE Trans. Circuit Syst. II, vol. 44, Sept. 1997, pp. 729-740 https://doi.org/10.1109/82.625005
  4. Tai-Cheng Lee and Behzad Razavi, 'A stabilization technique for phase-locked frequency synthesizers,' IEEE J, Solid-State Circuits., vol. 38, NO.6, June 2003, pp. 888-894 https://doi.org/10.1109/JSSC.2003.811879
  5. F.M GARDNER, Phaselock techniques, John Wiley &Sons, New York, 1979
  6. Dean Banerjee, ' An Analysis and Performance Evaluation of a Passive Filter Design Techniques for charge pump PLL's,' Application Note 1001, National Semiconductor Corporation, July 2001