A Low Noise Phase Locked Loop with Cain-boosting Charge Pump

Cain-boosting 전하펌프를 이용한 저잡음 위상고정루프

  • 최영식 (부경대학교 전자컴퓨터정보통신공학부) ;
  • 한대현 (동의대학교 전자공학과)
  • Published : 2005.04.01

Abstract

In this paper, a gain-boosting charge pump(CP) and a latch type voltage controlled oscillato.(VCO) with voltage controlled resistor(VCR) were proposed. The gain-boosting CP achieves good .current matching of less than 11$mu$V voltage difference between 43$mu$V and 32$mu$V in its output range from 0.8V to 2.3V. The VCO with VCR shows good linear characteristics over the range from 1V to 3V. The fabricated VCO exhibits -108dBc/Hz phase noise at a 100kHz and is comparable to that of the integrated LC-tank oscillator. The phase locked loop(PLL) with new circuits was simulated in a 0.35$mu$m CMOS process and showed 150$mu$s locking time.

본 논문에서는 gain-boosting 회로를 이용하여 전류 미스매치를 줄일 수 있는 전하펌프와 전압제어 저항기를 사용하여 선형성이 우수한 래치 구조의 전압제어발생기를 제안하여 위상고정루프를 설계하였다. Cain-boosting 전하펌프를 사용한 위상고정루프는 루프필터 출력 전압 구간에서 11$mu$V(최대 43$mu$V, 최소 32$mu$V)의 전압 흔들림 차이를 나타내었다. 전압제어저항기를 이용한 전압제어발진기는 입력전압 동작 구간에서 우수한 선형성을 나타내었다. 또한 제작된 전압제어발진기의 위상 잡음 특성은 -1084Bc/Hz(a)100kHz이며 CMOS 공정으로 만들어진 LC 전압제어발진기와 비슷한 성능을 가진다. 0.35$mu$m CMOS 공정으로 시뮬레이션 하였으며 록킹 시간은 150$mu$s이다.

Keywords

References

  1. Hee-Tae Ahn, David J. Allstot, 'A Low Jitter 1.9-V CMOS PLL for UltraSPARC Microprocessor Applications', IEEE J. Solid-State Circuits, 2000, Mar., vol. 35, pp. 450-454 https://doi.org/10.1109/4.826829
  2. IIya I. Novof, John Austin, Ram Kellar, Don Strayer and Steve Wyatt, 'Fully Integrated CMOS Phase-Locked Loop with 15 to 240MHz Locking Range and $\{mp}50ps$ Jitter', IEEE J. Solid-State Circuits, 1995, Nov., vol. 30, pp. 1259-1266 https://doi.org/10.1109/4.475714
  3. Won-Hyo Lee, Jun-Dong Cho and Sung-Dae Lee, 'A high speed and low power phase-frequency detector and charge-pump', Design Automation Conf erence, 1999. Proceedings of the ASP-D AC '99. Asia and South Pacific, 18-21 Jan. 1999 , pp. 269 - 272 vol.1
  4. Bram De Muer and Michel S. J. Steyaert, ,A CMOS Monolithic ${\Delta}{\Sigma}$ -Controlled Fractional-N Frequency Synthesizer for DCS-1800', IEEE J. Solid-State Circuits, 2002, Jul., vol. 37, pp. 835-844 https://doi.org/10.1109/JSSC.2002.1015680
  5. Ian A Young, 'A PLL clock generator with 5 to 110 MHz of clock range microprosessors', IEEE J. Solid-State Circuits, 1992, Nov., vol. 27, pp. 1599-1 607 https://doi.org/10.1109/4.165341
  6. Jae-Shin Lee, Min-Sun Keel, Shin-II Lim and Suki Kim, 'Charge pump with perfect current matching characteristics in phase-locked loops', Electronics Letters, 2000, Nov, vol. 36, pp. 1907- 1908 https://doi.org/10.1049/el:20001358
  7. Behzad Razavi, Design of Analog CMOS Integrated Circuits. International Edition : McGraw-Hill 2001
  8. Chan-Hong Park and B. Kim, 'A Low-No ise, 900-MHz VCO in a $0.6-{\mu}m$ CMOS', IEEE J. Solid-State Circuits, 1999, May, vol. 34, pp. 586-591 https://doi.org/10.1109/4.760367
  9. Tai-Cheng Lee and Behzad Razavi.: 'A Stabilization technique for Phase-Locked Frequency Synthesizers', IEEE J. Solid State Circuits, June 2003, vol. 38, NO. 6, pp. 888-894 https://doi.org/10.1109/JSSC.2003.811879