Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A Low-power EEPROM design for UHF RFID tag chip

UHF RFID 태그 칩용 저전력 EEPROM설계

  • Published : 2006.03.01
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Abstract

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

본 논문에서 는 플래쉬 셀을 사용하여 수동형 UHF RFID 태그 칩에 사용되는 저전력 1Kb 동기식 EEPROM을 설계하였다. 저전력 EEPROM을 구현하기 위한 방법으로 다음과 같은 4가지 방법을 제안하였다. 첫째, VDD(=1.5V)와 VDDP(=2.5V)의 이중 전원 공급전압 방식을 사용하였고, 둘째, 동기식 회로 설계에서 클럭(clock) 신호가 계속 클럭킹(clocking)으로 인한 스위칭 전류(switching current)가 흐르는 것을 막기 위해 CKE(Clock Enable) 신호를 사용하였다. 셋째, 읽기 사이클에서 전류 센싱(current sensing) 방식 대신 저전력 소모를 갖는 clocked inverter를 사용한 센싱 방식을 사용하였으며, 넷째, 쓰기 모드시 Voltage-up 변환기(converter) 회로를 사용하여 기준전압 발생기(Reference Voltage Generator)에는 저전압인 VDD를 사용할 수 있도록 하여 전력 소모를 줄일 수가 있었다. $0.25{\mu}m$ EEPROM 공정을 이용하여 칩을 제작하였으며, 1Kb EEPROM을 설계한 결과 읽기 모드와 쓰기 모드 시에 소모되는 전력은 각각 $4.25{\mu}W$와 $25{\mu}W$이고, 레이아웃 면적(layout area)은 $646.3\times657.68{\mu}m^2$이다.

Keywords

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