동작적 모델 검증의 상위 레벨 사건에 대한 검출률 측정법

Coverage metrics for high-level events in behavioral model verification

  • 김강철 (전남대학교 공학대학 컴퓨터공학과) ;
  • 임창균 (전남대학교 공학대학 컴퓨터공학과) ;
  • 류재흥 (전남대학교 공학대학 컴퓨터공학과) ;
  • 한석붕 (경상대학교 공과대학 전자공학과)
  • 발행 : 2006.03.01

초록

최근에 CAD 툴의 비약적인 발전으로 인하여 대부분의 디지털 회로들은 VHDL 언어를 사용하여 설계된다. 그리고 IC 공정기술의 발달에 따라 하나의 칩에 많은 회로를 포함할 수 있으므로 VHDL 코드의 크기가 방대해져 이에 대한 검증(verification)은 칩 설계에 있어서 어렵고, 많은 시간을 소모하는 과정이 되고 있다. 본 연구에서는 SoC용 IP 사이에서 발생할 수 있는 자원충돌과 프로토콜의 오류를 검증하는 새로운 방법을 제시한다. VHDL 모델의 블록 또는 SoC용 IP 사이에서 발생할 수 있는 상위레벨 고장을 정의하고 분류하고, 하위 레벨 검증(low-level code verification)에 사용되는 검출률 측정 법을 사용하여 IP사이에서 발생하는 데이터 충돌과 프로토콜 또는 알고리즘의 오류를 검증하는 방법을 제안한다.

The complexity of IC has rapidly increased as VLSI fabrication technology has grown up quickly. This paper proposes verification methods for data conflicts and protocol between IPs for SoC with coverage metrics. The high-level events is defined to cooperation between blocks or process statement in HDL, or a sequence of performing a job compared to low-level event. They are classified into two categories, resource conflicts and protocol or specification-dependent conflicts. And two coverage metrics used for code coverage in low-level event are proposed to verify the hish-level events. The events of resource conflicts can be detected by using statement coverage metric if global signal or variable has flags in a testbench program, and protocol-dependent events can be checked by data flow metric or path metric.

키워드

참고문헌

  1. Jen- Tien Yen and Qichao Richard Yin, 'Multiprocessing Design Verification Methodology for Motorola MPC74XX PowerPC Microprocessor,' DAC, pp 718-723, 2000
  2. Cindy Eisner, et ai, 'A Methodology for Formal Design of Hardware Control with Application to Cache Coherence Protocols,' DAC, pp 724-729, 2000
  3. Kazuyoshi Kohno, Nobu Matsumoto, 'A New Verification Methology for Complex Pipeline Behavior,' DAC, pp. 816-821, 2001
  4. Wooseung Yang, Moo-Kyeong Chung and ChongpMin Kyung, 'Current Status and Challenges of Soc Verification for Embedded Systems Market,' IEEE, pp. 213-216, 2003
  5. Kangchul Kim, 'Efficient methods for reducing clock cycles in VHDL model verificatoin,' Journal of Electronics Engineers of Korea, V.40-SD, pp39-45, Dec. 2003
  6. Michael Keating and Pierre Bricaud, Reuse Methodology Manual, Kluwer Academic Publishers, 1998
  7. Amjad Hajjar and Tom Chen, 'An Accurate Forecasting Model for Behavioral Model Verification,' Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications, 2002
  8. Janick Bergeron, Writing Testbenches : Functional Verification of HDL models, 2nd edition, Kluwer Academic Publishers, 2003
  9. Qiushang Zhang and Ian G. Harris, 'A Data Flow Fault Coverage Metric For Validation of Behavioral HDL Descriptions', ICCAD, pp. 369-372, 2000
  10. Rolf Drechsler and Bernd Becker, Binary Design Diagrams : Theory and Implementation, Kluwer Academic Publishers, 1998
  11. Edmund M. Clarke, Orna Grumberg, Doron A. Peled, Model Checking, MIT Press, 2000
  12. Hoon Choi, Byeongwhee Yun, Yuntae Lee, and Hyungglae Roh, 'Model Checking of S3C2400X Industrial Embedded SoC Product,' DAC, pp. 611-616. 2001
  13. Kevin Skahill, 'A Designer's guide to VHDL design and verification', Electronic design, pp. 149-152, Feb. 19, 1996
  14. W. Howden, 'Confidence-based reliability and statistical coverage estimation', ISSRE'97, pp 283-291, Nov, 1997
  15. B. Dickinson, S. Shaw, 'Software techniques applied to VHDL design', New Electronics, N9, pp 63-65, May 1995
  16. Jim Lipman, 'Covering your HDL chip-design bets', EDN, pp 65-74. Oct. 1998
  17. Martin Abraham, et al, 'Optimize ASIC testsuite using code coverage analysis', EDN, pp. 149-152, Mat 21, 1998
  18. Brian Barrera, 'Code coverage analysis-essential to a safe design', Electronic Engineering, pp 41-43, Nov. 1998
  19. Daniel Geist, et. al, 'A Methodology for the verification of on a System on chip', DAC, pp 574-579, 1999
  20. Gilly Nativ, et. al, 'Cost evaluation of coverage directed test generation for the IBM Mainframe', ITC, pp 793-801, 2001
  21. John D. Carpinelli, Computer Systems Organization and Architecture, Addison Wesley, 2000