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Threshold Voltage Control of Pentacene Thin-Film Transistor with Dual-Gate Structure

  • Koo, Jae-Bon (Electronics and Telecommunications Research Institute) ;
  • Ku, Chan-Hoe (Electronics and Telecommunications Research Institute) ;
  • Lim, Sang-Chul (Electronics and Telecommunications Research Institute) ;
  • Lee, Jung-Hun (Electronics and Telecommunications Research Institute) ;
  • Kim, Seong-Hyun (Electronics and Telecommunications Research Institute) ;
  • Lim, Jung-Wook (Electronics and Telecommunications Research Institute) ;
  • Yun, Sun-Jin (Electronics and Telecommunications Research Institute) ;
  • Yang, Yong-Suk (Electronics and Telecommunications Research Institute) ;
  • Suh, Kyung-Soo (Electronics and Telecommunications Research Institute)
  • Published : 2006.09.24
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Abstract

This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

Keywords

References

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