Journal of Welding and Joining

  • 제24권2호
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  • Pages.64-70
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  • 2006
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  • 2466-2232(pISSN)
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  • 2466-2100(eISSN)
대한용접접합학회 (The Korean Welding and Joining Society)
권호 표지

3D 패키지용 관통 전극 형성에 관한 연구

Fabrication of Through-hole Interconnect in Si Wafer for 3D Package

  • 김대곤 (성균관대학교 공과대학 신소재공학부) ;
  • 김종웅 (성균관대학교 공과대학 신소재공학부) ;
  • 하상수 (성균관대학교 공과대학 신소재공학부) ;
  • 정재필 (서울시립대학교 공과대학 신소재공학과) ;
  • 신영의 (중앙대학교 기계공학부) ;
  • 문정훈 (수원과학대학 일렉트로닉스패키징과) ;
  • 정승부 (성균관대학교 공과대학 신소재공학부)
  • Kim, Dae-Gon (School of Advanced Materials Science and Engineering, Sungkyunkwan University) ;
  • Kim, Jong-Woong (School of Advanced Materials Science and Engineering, Sungkyunkwan University) ;
  • Ha, Sang-Su (School of Advanced Materials Science and Engineering, Sungkyunkwan University) ;
  • Jung, Jae-Pil (Department of Materials Science Engineering, Seoul University) ;
  • Shin, Young-Eui (School of Mechancal Engineering, Chung-Ang University) ;
  • Moon, Jeong-Hoon (Department of Electronic Packaging) ;
  • Jung, Seung-Boo (School of Advanced Materials Science and Engineering, Sungkyunkwan University)
  • 발행 : 2006.04.01
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초록

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

키워드

참고문헌

  1. K. N.Tu and K Zeng : Tin-Lead(SnPb) solder reaction in flip chip technology, Materials Science and Engineering R, 34. (2001), 1-58 https://doi.org/10.1016/S0927-796X(01)00029-8
  2. Jong-Woong Kim, Dae-Gon Kim, Won Sik Hong and Seung-Boo Jung Evaluation of Solder Joint Reliability in Flip-Chip Packages during Accelerated Testing. Journal of Electronic Materials. 34-12. (2005), 1550- 1557 https://doi.org/10.1007/s11664-005-0177-3
  3. Frank Stepniak : Failure criteria of flip chip joints during accelerated testing, Microelectronics Reliability. 42-12. (2002), 1921-1930 https://doi.org/10.1016/S0026-2714(02)00121-X
  4. Dae-Gon Kim. Jong-Woong Kim, Jung-Goo Lee, Hirotaro Mori, David J. Quesnel and Seung-Boo Jung : Solid state interfacial reaction and joint strength of Sn-37Pb solder with Ni-P under bump metallization in flip chip application, 395, (2005), 80-87 https://doi.org/10.1016/j.jallcom.2004.11.038
  5. Jong-Woong Kim and Seung-Boo Jung : Optimization of shear test for flip chip solder bump using 3-dimensional computer simulation. Microelectronic Engineering. 82. (2005). 554-560 https://doi.org/10.1016/j.mee.2005.07.055
  6. L. K. Teh. E. Anto, C. C. Wong, S. G. Mhaisalkar, E. H. Wong, P. S. Teo and Z. Chen: Development and reliability of non- conductive adhesive flip-chip packages. Thin Solid Films. 462-463. (2004). 446 -453
  7. Rao. R. Tummala: SOP: What IS IT and Why- A New Microsystem integration Technology Paradigm-Moore' Law for System Integration of Miniaturized Convergent Systems of the Next Decade. IEEE TRANSACTIONS ON ADVANCED PACKAGING. 27-2, (2004), 241- 249 https://doi.org/10.1109/TADVP.2004.830354
  8. Horoshi Yamada. Takashi Togasaki, Masanobu Kimura. and Hajime Sudo : High-Density 3-D Packaging Technology Based on the Sidewall Interconnection Method and Its Application for CCD Micro Camera Visual Inspection System. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 26-2, (2003). 113-121 https://doi.org/10.1109/TCAPT.2003.811464
  9. Gerard Kelly, Anthony Morrissey, John Alderman and Henri Camon : 3-D Packaging Methodologies for Microsystem. IEEE TRANSACTIONS ON ADVANCED PACKAGING. 23-4. (2000), 623-630 https://doi.org/10.1109/6144.833038
  10. Kris Kwiatkiwski. Robert Wojnarowski. Chris Kapusta. Stuart Kleinfeder and Mark Wilke : 3-D Electronics Interconnect for High-Performance Imaging Detectors. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 51-4, (2004). 1829-1834
  11. Hyoung Soo Ko, Jin S, Kim, Hyun Gook Yoon. Se Young -Jang, Sung Dong, Cho and Kyung Wook Paik : Development of Three-Dimensional Memory Die Stack Package Using Polymer Insulated Sidewall Technique, IEEE TRANSACTIONS ON ADVANCED PACKAGING, 23-2, (2000), 252-256 https://doi.org/10.1109/6144.833038
  12. Y. K. Tsuiand and S. W. Ricky : Design and Fabrication of a Flip-Chip-on-Chip 3-D Packaging Structure With a Through-Silicon Via for Underfill Dispensing, IEEE TRANSACTIONS ON ADVANCED PACKAGING, 51-4, (2004), 413-420
  13. Jesus N. Calata, John G. Bai, Xingsheng Liu, Sihua Wen, and Guo-Quan Lu : Three- Dimensional Packaging for Power Semiconductor Devices and Modules, IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28-3, (2005), 404-412 https://doi.org/10.1109/TADVP.2005.852837
  14. Leonard W. Schaper, Susan L. Burkett, Silke Spiesshoefer. Gowtham V. Vangara, Ziaur Rahman, and Swetha Polamreddy : Architectural Implocations and Process Development of 3-D VLSI Z-Axis Interconnects Using Through Silicon Vias, IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28-3 (2005), 356-366 https://doi.org/10.1109/TADVP.2005.853271
  15. Vaidyanathan Kripesh, Seung Wook Yoon, V. P. Ganesh, Navas Khan, Mihai D, Rotaru, Wang Fang, and Mahadevan K. Iyer : Three-Dimensional System-in-Package Using Stacked Silicon Platform Technology, IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28-3. (2005), 377-386
  16. Brian Morgan, Xuefeng Hua. Tomohiro Iguchi. Taizo Tomioka. Gottieb S. Oehrlein and Reza Ghodssi : Substrate interconnect technologies for 3-D MEMS packaging, Microelectronics Engineering, 81. (2005) 106-116 https://doi.org/10.1016/j.mee.2005.04.004
  17. Kazumi hara. Yohei Korashima, Nobuaki Hashimoto, Kuniyasu Matsui, Yoshihide Matsuo, Ikuya Miyazawa, Tomonaga Kobayashi, Yoshihiko Yokoyama, and Motohiko Fukazawa : Optimization for Chip Stack in 3-D Packaging, IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28-3, (2005), 367-376 https://doi.org/10.1109/TADVP.2005.852978
  18. Gun-Ho Chang, Si-Young Chang and Jae-Ho Lee : Via/Hole Filling by Pulse-Reverse Copper Electroplating For 3D SiP, Materials Science Forum, 510-511, (2006), 942-945 https://doi.org/10.4028/www.scientific.net/MSF.510-511.510