대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

PRML 신호용 저 전력 아날로그 병렬처리 비터비 디코더 개발

Fabrication of a Low Power Parallel Analog Processing Viterbi Decoder for PRML Signal

  • Kim Hyun-Jung (Division of Electronics and Information Engineering, Chonbuk National University) ;
  • Son Hong-Rak (Samsung Advanced Institute of Technology) ;
  • Kim Hyong-Suk (Division of Electronics and Information Engineering, Chonbuk National University)
  • 발행 : 2006.06.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

DVD용 PRML신호를 디코딩할 수 있는 병렬 아날로그 비터비 디코더를 칩으로 제작하고 테스트 결과를 기술하였다. 병렬 아날로그 비터비 디코더는 기존의 디지털 비터비 디코더를 아날로그 병렬처리 회로를 이용하여 구현한 것으로, 전력 소모가 매우 적다는 장점이 있다. 본 연구에서는 제안한 순환형 아날로그 비터비 디코더 회로를 DVD의 PRML 신호 디코딩용으로 설계 제작하였고, 그 상세 설계 내용과 각 회로의 신호 특성을 분석하였으며, 이를 기반으로 향후 개선 사항을 기술하였다. 또한, 칩으로 제작된 회로가 동작하여 PRML용 신호가 잘 디코딩됨을 보였다.

A parallel analog Viterbi decoder which decodes PRML signal of DVD has been fabricated into a VLSI chip. The parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. In this paper, the analog parallel Viterbi decoding technology is applied for the PRML signal decoding of DVD. The benefits are low power consumption and less silicon consumption. The designed circuits are analysed and the test results of the fabricated chip are reported.

키워드

참고문헌

  1. H. Kobayashi and D. T. Tang, 'Application of partial response channel coding to magnetic recording system,' IBM Journal of Research and Development, pp, 368-375, 1970 https://doi.org/10.1147/rd.144.0368
  2. R. D. Ciderciyan, F. Dolvio, R.Hermann, W. Hirt, and W. Schoot, 'A PRML system for digital magnetic recording,' IEEE J. on Selected Area Communication, Vol 10, no. 1, pp. 38-56, 1992 https://doi.org/10.1109/49.124468
  3. F. Dolvio, 'Signal processing for high-density digital magnetic recording,' Proc, VLSI and Computure Peripherals, pp. 1.91-1.96, 1989 https://doi.org/10.1109/CMPEUR.1989.93353
  4. S. Sridharan and L. R. Carley, 'A 100-MHz 350-mW 0.6um CMOS 16-state generalizedtarget' Viterbi detector for disk-drive read channels,' IEEE J. Solid-State Circuits, vol. 35, pp. 362-370, Mar. 2000 https://doi.org/10.1109/4.826818
  5. K. He and G. Cauwenberghs, 'Integrated 64-state parallel analog Viterbi decoder,' Proceedings of ISCAS 2000, Geneva, Swiss, vol. IV, pp. 761-764 https://doi.org/10.1109/ISCAS.2000.858863
  6. Sung Han Choi, Jun Jin Kong, Byung Gook Chung, Yong Hwan Kim, 'Viterbi Detector Architeucture for High Speed Optical Storage,' 1997 IEEE TENCON-Speech and Image Technologies for Computing and Telecommunications, pp 89-92, 1997 https://doi.org/10.1109/TENCON.1997.647265
  7. G. D. Forney, JR. 'The Viterbi Algorithm,' Proc. of the IEEE, vol. 61, No.3, Mar. 1973 https://doi.org/10.1109/PROC.1973.9030
  8. A. J. Viterbi, 'Error bounds for convolutional codes and an asymptotically optimun decoding algorithm,' IEEE Tr. on' Information Theory, vol.13, pp.260-269, 1967 https://doi.org/10.1109/TIT.1967.1054010
  9. S. Mital and Y. Ouchi, 'A 150Mb/s PRML chip for magnetic disk dirve,' IEEE International Solid-State Circuits Conference, San Francisco, CA, FEB, pp 62-63, 1996 https://doi.org/10.1109/ISSCC.1996.488514
  10. G. T. Tuttle and G. D. Visshakhadatta, 'A 130Mb/s PRML read/write channel with digital-servo detection,' International Solid-State Circuits Conference, Sanfrancisco, CA, FEB, pp64-65, 1996 https://doi.org/10.1109/ISSCC.1996.488515
  11. K. Parsi and N. Rao, 'A 200M/s PRML read/write charmel IC.,' International Solid-State Circuits Conference, San Francisco, CA, FEB pp 66-67, 1996 https://doi.org/10.1109/ISSCC.1996.488516
  12. Hyongsuk Kim, Hongrak Son, Tamas Roska, Leon. O. Chua, 'Optical path finding with space-and time-variant metric weights with Multi-layer CNN,' Int. J. Circ. Theor, Appl., Vol. 30, pp.247-270, Feb. 2002 https://doi.org/10.1002/cta.199
  13. Hyongsuk Kim, Hongrak Son, Tamas Roska, and Leon O. Chua, 'High-Performance Viterbi Decoder With Circularly Connected 2-D CNN Unilateral Cell Array,' IEEE Transactions on Circuits and Systems I, Vol.52,pp. 2208- 2218, Oct 2005 https://doi.org/10.1109/TCSI.2005.853263