The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
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Design of a Parallel Rendering Processor Architecture with Effective Memory System

효과적인 메모리 구조를 갖는 병렬 렌더링 프로세서 설계

  • 박우찬 (세종대학교 컴퓨터공학과) ;
  • 윤덕기 (세종대학교 컴퓨터공학과) ;
  • 김경수 (세종대학교 컴퓨터공학과)
  • Published : 2006.08.01
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Abstract

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. For the above two goals, effective memory organizations including a new pixel cache architecture are presented. The experimental results show that the proposed architecture achieves almost linear speedup at best case even in sixteen rasterizers.

현재의 거의 대부분의 3차원 그래픽 프로세서는 한 개의 삼각형을 빠르게 처리하는 구조로 되어 있으며, 향후 여러 개의 삼각형을 병렬적으로 처리할 수 있는 프로세서가 등장할 것으로 예상된다. 고성능으로 삼각형을 처리하기 위해서는 각 래스터라이저마다 고유한 픽셀 캐시를 가져야 한다. 그런데, 병렬로 처리되는 경우 각각의 프로세서와 프레임 메모리 간에 일관성 문제가 발생할 수 있다. 본 논문에서는 각각의 그래픽 가속기에 픽셀 캐시를 사용가능 하게 하면서 성능을 증가시키고 일관성 문제를 해결하는 병렬 렌더링 프로세서를 제안한다. 제안하는 구조에서는 픽셀 캐시 미스에 의한 지연(latency)을 감소시켰다. 이러한 2가지 성과를 위하여 현재의 새로운 픽셀 캐시 구조에 효과적인 메모리 구조를 포함시켰다. 실험 결과는 제안하는 구조가 16개 이상의 래스터라이저에서 거의 선형적으로 속도 향상을 가져옴을 보여준다.

Keywords

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