Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지

Clock Distribution in High-Performance System Design

고성능 시스템 설계에서의 클럭 신호 분배

  • Jeong Tai-Kyeong.T (Department of Electrical and Computer Engineering, the University of Texas) ;
  • Lee Jang-Ho (Department of Electrical and Computer Engineering, the University of Texas)
  • Published : 2006.09.01
Download PDF
⟨ Previous Next ⟩

Abstract

The problem of reducing power dissipation while simultaneously delivering acceptable levels of performance is becoming a critical concern in high pelf[mann system design. In this paper, we present this power dissipation problem from the clock generation and distribution side. We examine clock power efficiency and several applications as well as wireless communication circuits.

수용 가능한 수준의 성능을 동시에 전달하고 분배하는 동안의 소비 전력을 줄이는 문제는 고성능 시스템의 설계분야에서는 더욱 더 결정 적 인 관심사로 받아지고 있다. 본 논문에서는 전력분배의 문제를 클럭 신호 발생과 분배의 관점에서 제시하고자 한다. 우리는 클럭 신호의 전력 효율성과 다른 응용제품 이외에도 무선통신의 회로에서도 찾아 검증하였다.

Keywords

References

  1. J. M. Rabaey, 'Low-Power Silicon Architecture for Wireless Communications,' ISSCC'94: IEEE International Solid-State Circuits Conference, Washington, 1994
  2. S. M. Kang, Y. Leblebici, 'CMOS Digital Integrated Circuits-Analysis and Design,' 2nd Edition McGraw-Hill International Edition. 1999 USA
  3. E. W. Dobberpuhl, 'A 200-MHz 64-b Dual-Issue CMOS microprocessor,' IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1115-1567, Nov 1992
  4. P. Hofstee, N. Aoki, et. al, 'A 1.0 GHz Single-Issue 64-Bit PowerPC Processor,' IEEE International Solid-State Circuits Conference, pp. 92-93, 2000
  5. W. C. Athas, and L. Svensson, 'Reversible Logic Issues in Adiabatic CMOS,' Proc. Workshop on Physics and Computation, pp. 111-118, Nov 1994
  6. K. J. Nowka, T. Galambos, 'Circuits design techniques for a Gigahertz Integer Microprocessor,' International Conference on Computer Design, pp. 11-16, Oct 1998
  7. W. C. Athas, et. al., 'A Low-Power Microprocessor Based on Resonant Energy,' IEEE J. Solid-State Circuits, vol. 32, no. 11, pp. 1693-1701, Nov 1997 https://doi.org/10.1109/4.641689
  8. B. A. Floyd, and K. K. O, 'The projected power consumption of a wireless clock distribution system and comparison to conventional distribution systems,' IEEE Int. Conf. Interconnect Technology, pp. 248-250 May 1999
  9. T. Jeong, A. Ambler, 'Power Efficiency System for Fligth Application (PESFA) Mission: Low Power Dissipation in Digital Circuit Design for Flgith Application/Space Communications,' IEEE Trans. Aerospace and Electrical Systems, vol 42, 2006
  10. A. Vittal, 'Low-power buffered clock tree design,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol, 16, no. 9, Sep 1997