Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of an 1.8V 6-bit 1GS/s 60mW CMOS A/D Converter Using Folding-Interpolation Technique

Folding-Interpolation 기법을 이용한 1.8V 6-bit 1GS/s 60mW 0.27$mm^2$ CMOS A/D 변환기의 설계

  • Jung, Min-Ho (Dept. of Semiconductor Science, Dongguk University) ;
  • Moon, Jun-Ho (Dept. of Semiconductor Science, Dongguk University) ;
  • Hwang, Sang-Hoon (Dept. of Semiconductor Science, Dongguk University) ;
  • Song, Min-Kyu (Dept. of Semiconductor Science, Dongguk University)
  • 정민호 (동국대학교 반도체과학과) ;
  • 문준호 (동국대학교 반도체과학과) ;
  • 황상훈 (동국대학교 반도체과학과) ;
  • 송민규 (동국대학교 반도체과학과)
  • Published : 2007.11.25
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Abstract

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

본 논문에서는, 1.8V 6-bit 1GSPS CMOS A/D 변환기를 제안한다. 제안하는 A/D 변환기는 저 전력소모를 위해 폴딩 구조의 A/D 변환기로 구현되었으며, 특히 전압구동 인터폴레이션 기법을 사용하여 전력소모를 최소화 하였다. 또한 전체 A/D 변환기의 전력소모 감소를 위해 새로운 폴더 감소회로를 제안하여 기존의 폴딩 A/D 변환기에 비해 폴더 및 프리앰프 수를 절반으로 줄였고, 새로운 프리앰프 평균화 기법과 폴딩에 적합한 레이아웃 기법을 제안하여 전체 A/D 변환기의 성능을 향상시켰다. 설계된 A/D 변환기는 1GSPS의 변환속도에서 500MHz의 ERBW를 가지며, 이때의 전력소모는 60mW이였다. 측정결과 INL은 $\pm$0.5 LSB, DNL은 $\pm$0.7 LSB 이내의 정적 특성을 보였으며 Fin=100MHz의 샘플링 300MHz에서 SNR=34.1dB의 동적 특성을 나타내었다. 제안하는 A/D 변환기는 0.18um CMOS공정으로 제작되었으며 ADC 코어의 유효 칩 면적은 $0.27mm^2$ 이다.

Keywords

References

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