Journal of the Korean Society for Railway (한국철도학회논문집)

The Korean Society for Railway (한국철도학회)
권호 표지

Mastership Passing Algorithm for Train Communication Network Protocol

철도 제어통신 네트워크 프로토콜에서 마스터권한 진달 기법

  • Published : 2007.02.28
Download PDF
⟨ Previous Next ⟩

Abstract

TCN(Train Communication Network) adopts the master/slave protocol to implement real-time communication. In this network, a fault on the master node, cased by either hardware or software failure, makes the entire communication impossible over TCN. To reduce fault detection and recovery time, this paper propose the contention based mastership transfer algorithm. Slave nodes detect the fault of master node and search next master node using the proposed algorithm. This paper also shows the implementation results of a SoC-based Fault-Tolerant MVB Controller(FT-MVBC) which includes the fault-detect-logic as well as the MVB network logic to verify this algorithm.

Keywords

References

  1. IEC 61375-1 Standard, Train Communication Network, 1999
  2. UIC 556 Standard, Information Transportation on the Train Bus 1999.05.01 v2.0
  3. H. Kirrmann and P.A. Zuber, 'IEC/IEEE Train Communication Network', 1996
  4. Jimenez, J.;Martin, J.L.; Cuadrado, C.;Arias, J.;Lazaro,J.; 'A top-down design for the train communication network', Industrial Technology, 2003 IEEE International Conference on Volume 2, 10-12 Dec. 2003 Page(s) 1000-1005
  5. Jimenez, J.;Martin, J.L.; Zuloaga, A.; Bidarte, U.;Arias,J; 'Comparison of two designs for the mutifunction vehicle bus' Computer -Aided Design of Integrated Circuits and System, IEEE Transactions on Volume 25, Issue 5, May 2006 Page(s):797-805 https://doi.org/10.1109/TCAD.2005.855925
  6. Moreno, J.C.; Laloya, E.J; Navarro,J; 'Line redundancy in MVB-TCN devices: a control unit design' Electrotechnical Conference, 2006. MELECON 2006. IEEE Mediterranean 16-19 May 2006 Page(s): 789-794
  7. Bricaud, P.J., 'IP reuse creation for system-on-a-chip design', Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 , 16-19 May 1999 Page(s): 395 -401
  8. Benini, L.; De Micheli,G., 'Networks on chips: a new SoC paradigm', Computer, Volume: 35 Issue: 1 , Jan. 2002 ,Page: 70 -78
  9. Lahiri, K.; Raghunathan, A.; Dey, S., 'Fast performance analysis of bus-based system-on-chip communication architectures', Comput er-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on , 7-11 Nov. 1999, Page(s): 566 -572
  10. Lahtinen, V.; Kuusilinna, K.; Hamalainen, T., 'Optimizing finite state machines for system-on-chip communication', Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , Volume: 1, 26-29 May 2002, Page(s): I-485-I-488 vol.1
  11. Lahiri, K.; Raghunathan, A.; Lakshminarayana,G;.Dey,S,; Dey, S.; 'Design of high-performance system-on-chips using communicat ion architecture tuners' Computer-Aided Design of Integrated Circuits and systems, IEEE Transactions on Volume 23, Issue 5, May 2004 Page(s):620-636 https://doi.org/10.1109/TCAD.2004.826585
  12. Sunghyun Lee; Sungjoo Yoo; Kiyoung Choi, 'Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model', Hardware/Software Codesign, 2002. CODES 2002. Proceedings of the Tenth International Symposium on , 6-8 May 2002, Page(s): 199 -204