Journal of the Institute of Electronics Engineers of Korea SP (대한전자공학회논문지SP)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient SAD Processor for Motion Estimation of H.264

H.264 움직임 추정을 위한 효율적인 SAD 프로세서

  • 장영범 (상명대학교 정보통신공학과) ;
  • 오세만 (상명대학교 정보통신공학과) ;
  • 김비철 (상명대학교 정보통신공학과) ;
  • 유현중 (상명대학교 정보통신공학과)
  • Published : 2007.03.25
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Abstract

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of H.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation and in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA(Field Programmable Gate Array) implementation results for the proposed structure show 39% and 32% gate count reduction in comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

이 논문에서는 H.264의 효율적인 움직임 추정을 위한 새로운 SAD(Sum of Absolute Differences) 프로세서의 구조를 제안하였다. SAD 프로세서는 전영역 탐색기법의 움직임 추정이나 고속 탐색기법의 움직임 추정에서 모두 사용되는 중요한 블록이다. 제안된 구조는 SAD 계산기 블록, combinator 블록, 최소값 계산기 블록의 3개의 블록으로 구성된다. 제안된 구조는 덧셈연산을 분산 연산(Distributed Arithmetic)을 사용하여 계산함으로써 구조를 단순화시켰다. 제안 구조를 HDL(Hardware Description Language)을 사용하여 실험한 결과 기존의 구조와 비교하여 39%의 게이트 카운트 감소효과를 보였다. 또한 FPGA를 사용하여 검증한 결과도 32%의 게이트 카운트 감소효과를 보였다. 따라서 제안된 움직임 추정용 SAD 프로세서는 칩의 면적이 중요한 변수인 H.264 칩에서 널리 사용될 수 있는 구조가 될 것이다.

Keywords

References

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