Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지
DOI QR코드

DOI QR Code

Analysis of Dimension-Dependent Threshold Voltage Roll-off and DIBL for Nano Structure Double Gate FinFET

나노구조 이중게이트 FinFET의 크기변화에 따른 문턱전압이동 및 DIBL 분석

  • Published : 2007.04.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.

본 연구에서는 나노구조 이중게이트 FinFET에 대하여 문턱전압이동 특성 및 드레인유기장벽저하(Drain Induced Barrier Lowering; DIBL)특성을 분석하였다. 분석을 위하여 분석학적 전류모델을 개발하였으며 열방사전류 및 터널링전류를 포함하였다. 열방사전류는 포아슨방정식에 의하여 구한 포텐셜분포 및 맥스월-볼쯔만통계를 이용한 캐리어분포를 이용하여 구하였으며 터널링 전류는 WKB(Wentzel-Kramers-Brillouin)근사를 이용하였다. 이 두 모델은 상호 독립적이므로 각각 전류를 구해 더함으로써 문턱 전압을 구하였다. 본 연구에서 제시한 모델을 이용하여 구한 문턱 전압 이동값이 이차원 시뮬레이션값과 비교되었으며 잘 일치함을 알 수 있었다. 분석 결과 10nm 이하에서 특히 터널링의 영향이 증가하여 문턱전압이동 및 DIBL이 매우 현저하게 나타남을 알 수 있었다. 이러한 단채널현상을 감소시키기 위하여 채널두께 및 게이트산화막의 두께를 가능한한 얇게 제작하여야함을 알았으며 이를 위한 산화공정개발이 중요하다고 사료된다.

Keywords

References

  1. H.R.Huff and P.M.Zeitzoff ,The Ultimate CMOS Device:A 2003 Perspective,' the 2003 International Conference on Characterization and Metrology for ULSI Technology, pp.l-16, Austin, Texas, 2003
  2. D.Hisamoto et al, 'FinFET-A Self- Aligned Double-Gate MOSFET Scalable to 20nm', IEEE Trans. Elec. Devices, Vol.47, No.12, pp.2320-2325, 2000 https://doi.org/10.1109/16.887014
  3. X.Huang et al, 'Sub-5Onm P-Channel FinFET', IEEE Trans. Elec. Devices, Vol.48 No.5, pp.880-885, 2001 https://doi.org/10.1109/16.918235
  4. Q.Chen, B.Agrawal, J.D.Meindl,'A Compre -hensive Analytical Subthreshold Swing(S) Model for Double-Gate MOSFETs,' IEEE Trans. Electron Devices, Vol. 49, no.6, pp.1086-1090, Jun, 2002 https://doi.org/10.1109/TED.2002.1003757
  5. D.Munteanu and J.L.Autran,'Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOl devices,' Solid-State Electronics, vol.47, pp.1219-1225, 2003 https://doi.org/10.1016/S0038-1101(03)00039-X
  6. M.Stadele, 'Influence of source-drain tunneling on the subthreshold behavior of sub-10nm double-gate MOSFETs,' ESSDERC Proc. , pp.-135-138, 2002
  7. H. K. Jung and S. Dimitrijev,'Analysis of Subthreshold Carrier Transport for Ultimate Double Gate MOSFET,' IEEE Trans. Electron Devices, Vol. 53, noA, pp. 685-691, 2006 https://doi.org/10.1109/TED.2006.870282