The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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DLL Design of SMD Structure with DCC using Reduced Delay Lines

지연단을 줄인 SMD 구조의 DCC를 가지는 DLL 설계

  • 홍석용 (전북대학교 공과대학 전자정보공학부 전자공학과) ;
  • 조성익 (전북대학교 공과대학 전자정보공학부) ;
  • 신홍규 (원광대학교 공과대학 전기전자및정보 공학부) ;
  • Published : 2007.06.01
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Abstract

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

Keywords

References

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