Korean Journal of Materials Research (한국재료학회지)

Materials Research Society of Korea (한국재료학회)
권호 표지
DOI QR코드

DOI QR Code

Overview of High Performance 3D-WLP

  • Kim, Eun-Kyung (Department of Nano-IT Engineering, Graduate School of Energy & Environment Seoul National University of Technology)
  • Published : 2007.07.27
Download PDF
⟨ Previous Next ⟩

Abstract

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

Keywords

References

  1. R. Reif, IEEE VLSL Systems, 12(4), 359-366 April (2004) https://doi.org/10.1109/TVLSI.2004.825833
  2. Eric Beyne, IEEE VLSI Technology, Systems, and Applications, p. 1-9 April (2006)
  3. K. Chen, M. kobrinsky, B. Barnett, R. Reif, IEEE Transaction on Electron Devices, 51(2), 233-239 Feb (2004) https://doi.org/10.1109/TED.2003.821567
  4. P. Morrow, M. Kobrinsky, M. Harmes, C. Park, S. Ramanathan, V. Ramachandrarao, H. Park, G Kloster, S. List, S. Kim, Proc. of AMC, 20, 125-130 Oct (2004)
  5. J. Balachandran, S. Brebels, G Carchon, M. Kuijk, W. De Raedt, B. Nauwelaers, and E. Beyne, IEEE VLSI SYstems, 14(6), 654-659 June (2006) https://doi.org/10.1109/TVLSI.2006.878229
  6. Eun-Kyung Kim, SEMICON Korea 2005, Proc. of SEMI Technical Symposium, p. 291-293, Feb 8-10 (2006)
  7. R. Tummaa, IEEE lCEPT, 30 Aug. - 2 Sept. (2005) P3-7
  8. S. Pozder, J-Q Lu, Y. Kwon, S. Zollner, J. Yu, J. McMahon, T.S. Cale, K. Yu, R. J. Gutmann, IEEE, lTC, p. 102-104 (2004)
  9. A. W. Topol, B. K. Furman, K. W. Guarini, L. Shi, G M. Cohen, G. F. Walker, IEEE, ECTC, p. 931-938 (2004)
  10. B. Black, D. W. Nelson, C. Webb, N. Samra, Proceedings of the IEEE, ICCD (2004)
  11. S. List, C. Webb, and S. Kim, Proc. of AMC, 18, p. 29-36 Oct (2002)
  12. K. Takahashi, H. Terao, Y. Tomita, Y. Yamaji, M. Hoshino, T. Sato, T. Morifuji, M. Sunohara, and M. Bonkohara, Jpn. J. Appl. Phys., 40, 3032-3037 (2001) https://doi.org/10.1143/JJAP.40.3032
  13. J. Joyner, P. Zarkech-Ha, J. Davis, and J. Meindl, lTC, Proc of IEEE, p. 126-128 (2000)
  14. A. Fan, A. Rahman, and R. Reif, Electrochemical and Solid State Letters, 2(10), 534-536 (1999) https://doi.org/10.1149/1.1390894
  15. Tezzason Semiconductor (http://www.tezzaron.com). 3D IC Industry Summary

Cited by

  1. TSV Liquid Cooling System for 3D Integrated Circuits vol.20, pp.3, 2013, https://doi.org/10.6117/kmeps.2013.20.3.001
  2. Evaluation of Si liquid cooling structure with microchannel and TSV for 3D application vol.23, pp.7, 2017, https://doi.org/10.1007/s00542-016-3009-x