Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A design of fractional-N phase lock loop

Fractional-N 방식의 주파수 합성기 설계

  • Published : 2007.08.31
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Abstract

In this paper, phase-locked loop (PLL) of a combinational architecture consisting of an adaptive bandwidth and fractional-N is presented to improve performances and reduce the order of ${\Delta}{\Sigma}$ modulator while maintaining equivalent or better performance with fast locking. The architecture of adaptive bandwidth PLL was simulated by HSPICE using 0.35m CMOS parameters. The behavioral simulation of the proposed adaptive bandwidth fractional-N PLL with a ${\Delta}{\Sigma}$ modulator was carried out by using MatLab to determine if the architecture could achieve the objectives. The HSPICE simulation showed that this type of PLL was able to fast locking, and reduce fractional spurs about 20dB.

논문은 fractional-N 방식의 주파수 합성기(PLL)를 낮은 차수의 ${\Delta}{\Sigma}$변조기로 더욱 높은 성능의 PLL로 설계하기 위하여 대역폭 가변 방식의 PLL과 ${\Delta}{\Sigma}$방식의 fractional-N PLL의 구조를 합성한 새로운 방식의 PLL을 제안한다. Matla으로 대역폭 가변을 이용한 ${\Delta}{\Sigma}$방식의 fractional-N PLL의 시뮬레이션을 수행하여 제안된 구조의 특성을 관찰하였다. 본 논문의 대역폭 가변 PLL은 HSPICE 0.35um CMOS 공정을 이용하여 시뮬레이션 하였고, 그 결과 제안된 PLL은 빠른 록이 가능하고 fractional spur를 20dB 정도 낮출 수 있었다.

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References

  1. B. Razavi, 'Challenges in the design of frequency synthesizers for wireless applications,' in Proc. IEEE Custom Integrated Circuits Conf., 1997, pp. 395-402
  2. T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, 'Delta-sigma modulation in fractional - N frequency synthesis,' IEEE j, Solid state Circuits, vol.35, PP. 1453-1460, Oct., 2000 https://doi.org/10.1109/4.871322
  3. W, Rhee, B. Song, and A. Ali, 'A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-bit third-order - modulator,' IEEE J, Solid-State Circuits, vol. 35, pp. 1453-1460, Oct., 2000 https://doi.org/10.1109/4.871322
  4. E. Temporiti, G. Albasini, R. Castello, and M. Colombo, 'A 700-KHz bandwidth fractional synthesizerwith spurs compensation and linearization techniques for WCDMA applications,' IEEE J, Solid-State Circuits, vol. 39, pp. 1446-1454, Sept., 2004 https://doi.org/10.1109/JSSC.2004.831598
  5. S. Pamarti, L. Jansson, and I. Galton, 'A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation,' IEEE J, Solid-State Circuits, vol. 39, pp. 49-62, Jan., 2004 https://doi.org/10.1109/JSSC.2003.820858
  6. S. E. Meninger and M. H. Perrot, 'A fractional-N synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise,' IEEE Trans. Circuits Syst. II, vol. 50, pp. 839-848, Nov., 2003 https://doi.org/10.1109/TCSII.2003.819114
  7. Joonsuk Lee, and Beomsup Kim, 'A low-noise fast locking phase-lockinged loop with adaptive bandwidth con ntrol,' IEEE J, Solid-State Circuits, vol. 35, pp.1137-1145, Aug. 2000 https://doi.org/10.1109/4.859502
  8. B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998