Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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The Construction of the Digital Logic Switching Functions using PLA

PLA에 기초한 디지털논리스위칭함수 구성

  • 박춘명 (충주대학교 전기.전자 및 정보공학부 컴퓨터공학과)
  • Published : 2008.10.30
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Abstract

This paper presents a method of constructing the digital logic switching functions using PLA. First of all, we propose a MIN and MAX algebra arithmetic operation based on the Post algebra. And we discuss the T-gate which is used for realization of the MIN and MAX algebra arithmetic operation. Next, we discuss the MIN array and MAX array which are basic circuit of the PLA, also we discuss the literal property. For the purpose of the design for the digital logic switching functions using PLA, we Propose the variable partition, modular structure design, literal generator, decoder and invertor. The proposed method is the more compactable and extensibility.

본 논문에서는 PLA를 사용하여 디지털논리 스위칭함수를 효과적으로 구성하는 방법을 제안하였다. 제안한 방법은 먼저 포스트 대수를 기반으로 MIN 대수연산과 MAX 대수연산을 제안하였고, 이를 구현하기 위해 T-gate에 대해 논의하였다. 그리고 PLA의 기본 회로인 MIN 배열, MAX 배열과 리터럴에 대해 논의하였다. PLA를 사용하여 디지털논리스위칭함수를 설계하기 위해 변수분할, 모듈러 구조, 리터럴 생성기, 복호기와 인버터를 제안하였다. 제안한 방법은 좀 더 콤펙트하고 확장성이 용이하다.

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References

  1. M.Davio, J.Deschamps and A.Thayse, Discrete and Switching Functions, McGraw-Hill Inc. 1978
  2. D. Green, Modern Logic Design, Addison wesely, 1986
  3. M.D.Ercegovac, and T.Lang, Digital Systems and hardware/Firmware Algorithms, John Wiley & Sons, 1985
  4. D.Lee, A.A. Gaffar, O.Mencer, and W.Luk, "Optimization Hardware Function Evaluation," IEEE Trans. Comput., vol.54, No.12, pp.1520-1531, Dec., 2005 https://doi.org/10.1109/TC.2005.201
  5. S.Mitra, N.R.Saxena, and E.J.McCluskey, "Efficient Design Diversity Estimation for Combinational Circuits," IEEE Trans. Comput., vol.53, No.11, pp.1483-1492, Nov., 2004 https://doi.org/10.1109/TC.2004.95
  6. T.Sasao, "Input variable assignment and output phase optimization of PLA's," IEEE Trans. Comput., vol. C-33, pp. 879-894, Oct. 1984 https://doi.org/10.1109/TC.1984.1676349
  7. H.L.Kuo and K.Y.Fang, "The multiple-valued programmable logic array and application in modular design," in Proc. ISMVL-85, pp.10-18. May 1985
  8. M.Kameyama,"Toward The Age of Beyond-Binary Electronics and Systems", IEEE Proc. 20th ISMVL, pp.162-166, May, 1990
  9. M.Nakajima and M.Kameyama,"Design of Highly Parallel Linear Digital System for ULSI Processors", IEICE Trans, Vol.E76-C, No.7, pp.1119-1125, July, 1993