The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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The Gain Enhancement of 1.8V CMOS Self-bias High-speed Differential Amplifier by the Parallel Connection Method

병렬연결법에 의한 1.8V CMOS Self-bias 고속 차동증폭기의 이득 개선

  • 방준호 (전북대학교 공과대학 응용시스템공학부)
  • Published : 2008.10.01
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Abstract

In this paper, a new parallel CMOS self-bias differential amplifier is designed to use in high-speed analog signal processing circuits. The designed parallel CMOS self-bias differential amplifier is developed by using internal biasing circuits and the complement gain stages which are parallel connected. And also, the parallel architecture of the designed parallel CMOS self-bias differential amplifier can improve the gain and gain-bandwidth product of the typical CMOS self-bias differential amplifier. With 1.8V $0.8{\mu}m$ CMOS process parameter, the results of HSPICE show that the designed parallel CMOS self-bias differential amplifier has a dc gain and a gain-bandwidth product of 64 dB and 49 MHz respectively.

Keywords

References

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