The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

An Efficient Scheduling Method based on Dynamic Voltage Scaling for Multiprocessor System

멀티프로세서 시스템을 위한 동적 전압 조절 기반의 효율적인 스케줄링 기법

  • Published : 2008.03.01
Download PDF
⟨ Previous Next ⟩

Abstract

The DVS(Dynamic Voltage Scaling) technique is the method to reduce the dynamic energy consumption. As using slack times, it extends the execution time of the big load operations by changing the frequency and the voltage of variable voltage processors. Researches, that controlling the energy consumption of the processors and the data transmission among processors by controlling the bandwidth to reduce the energy consumption of the entire system, have been going on. Since operations in multiprocessor systems have the data dependency between processors, however, the DVS techniques devised for single processors are not suitable to improve the energy efficiency of multiprocessor systems. We propose the new scheduling algorithm based on DVS for increasing energy efficiency of multiprocessor systems. The proposed DVS algorithm can improve the energy efficiency of the entire system because it controls frequency and voltages having the data dependency among processors.

Keywords

References

  1. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Kluwer Academic, 2002.
  2. A. P.Chandrakasan, A. P. Sheng, and R. W. Brodersen, "Low-Power CMOS Digital Design," IEEE Journal of Solid-State Circuits, Vol. 27, No .4, pp. 473-484, 1992. https://doi.org/10.1109/4.126534
  3. G. Wei, J. Kim, D. Liu, S. Sidiropoulos, and M. Horowitz, "A variable-frequency parallel I/O interface with adaptive power-supply regulation," IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, pp. 1600-1610, Nov. 2000. https://doi.org/10.1109/4.881205
  4. Y. Shin, K. Choi, and T. Sakurai, "Power Optimization of real-Time Embedded Systems on Variable Speed Processors," in Proceedings of the International Conference on Computer-aided Design, pp. 365-368, Nov. 2000.
  5. L. Shang, L.-S. Peh, and N. K. Jha, "Dynamic voltage scaling with links for power optimization of interconnection networks," in Proceedings High-performance Computer Architecture Symposium, pp. 91-102, 2003.
  6. M. PEDRAM AND J. M. RABAEY, Power Aware Design Methodologies, Kluwer Academic, 2002.
  7. J. Luo, N. K. Jha, L.-S. Peh, "Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems," IEEE Transactions of Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 4, pp 427-437, Apr. 2007. https://doi.org/10.1109/TVLSI.2007.893660
  8. Axel Jantsch, Hannu Tenhunen, Networks on Chip, Kluwer Academic, ch. 3, 2003
  9. T. Burd and R. Brodersen, "Energy Efficient CMOS Microprocessor Design," in Proceedings of Hawaii International Conference on System Sciences, 1995.
  10. J. Kim and M. Horowitz, "Adaptive supply serial links with sub-1 V operation and per-pin clock recovery," IEEE Journal of Solid-State Circuits, Vol. 37, pp. 1403-1413, Nov. 2002. https://doi.org/10.1109/JSSC.2002.803937
  11. A. Chilambuchelvan, S. Saravanan and J.Raja Paul Perinbam, "A Simulation Software Development for Performance Analysis of DVS Algorithm for Low Power Embedded System," IEEE Transactions of Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 2, pp.173-182, Feb. 2006. https://doi.org/10.1109/TVLSI.2005.863747
  12. L. Kiss and A. R. Várkonyi-Kóczy, "A Hybrid Autonomous Robot Navigation Method Based on Artificial Intelligence and Soft Computing Techniques," in Proceedings of IFAC International Conference on Intelligent Control Systems and Signal Processing, Apr. 2003.