Scan Cell Grouping Algorithm for Low Power Design

  • Kim, In-Soo (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Min, Hyoung-Bok (School of Information and Communication Engineering, Sungkyunkwan University)
  • Published : 2008.03.01


The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.


  1. Laung-Terng Wang, Cheng-Wen Wu and Xiaoqing Wen, 'VLSI Test Principles and Architectures, Design For Testability', Elsevier Inc., 2006
  2. Ozgur Sinanoglu, Ismet Bayraktaroglu and Alex Orailoglu, 'Scan Power Reduction Through Test Data Transition Frequency Analysis', International Test Conference, pp. 844-850, 2002
  3. Ozgur Sinanoglu, Ismet Bayraktaroglu and Alex Orailoglu, 'Test Power Reduction Through Minimization of Scan Chain Transitions', Proceedings of the $20^th$ IEEE VLSI Test Symposium (VTS'02), 2002
  4. Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer and Jacob White, 'Estimation of Average Switching Activity in Combinational and Sequential Circuits', $29^th$ ACM/IEEE Design Automation Conference, pp. 253-259, 1992
  5. M. L. Bushnell, and V. D. Agrawal, 'Essentials of Electronic Testing', Academic publishers, 2000
  6. Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz and Sudhakar Reddy, 'Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application', IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 12, DECEMBER, PP. 1325-1333, 1998
  7. F. Brglez, D. Bryant and K. Kozminski, 'Combinational Profiles of Sequential Benchmark Circuits', IEEE Int. Symp. On Circuits and Systems, pp. 1929-1934, 1989
  8. Pran Kurup, and Taher Abbasi, 'Logic Synthesis using SYNOPSYS $2^nd$', Kluwer Academic Publishers, Massachusetts, 1997
  9. S. Wang and S. K. Gupta, 'ATPG for heat dissipation minimization during test application', International Test Conference, pp. 250-258, 1998
  10. H. J. Wunderlich and S. Gerstendorfer, 'Minimized power consumption for scan based BIST', International Test Conference, pp. 85-94, 1999
  11. F. Brglez, D. Bryan and K. Kozminski, 'Combinational Profiles of Sequential Benchmark Circuits', IEEE ISCAS, vol. 14, n. 2, pp. 1929-1934, May 1989
  12., 2006
  13. TetraMAX ATPG User Guide, Version 2000-11, Synopsys Inc., 2000
  14. TetraMAX Release Note, Version 2000-11, Synopsys Inc., 2000
  15., 2006
  16. compiler.html, 2006
  17., 2006
  18. Sangwook Cho and Sungju Park, 'A new synthesis technique of sequential circuits for low power and testing', Current Applied Physics, Volume 4, Issue 1, pp. 83-86, February 2004
  19. Hyungwoo Lee, Hakgun Shin and Juho Kim, 'Unified low power optimization algorithm by gate freezing, gate sizing and buffer insertion', Current Applied Physics, Volume 5, Issue 4, pp. 378-380, May 2005