Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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SA-Based Test Scheduling to Reduce the Test Time of NoC-Based SoCS

SA 기법 응용 NoC 기반 SoC 테스트 시간 감소 방법

  • 안진호 (호서대학교 전자공학과) ;
  • 김홍식 (연세대학교 전기전자공학과) ;
  • 김현진 (연세대학교 전기전자공학과) ;
  • 박영호 (한국전자통신연구원 NoC 기술팀) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2008.02.25
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Abstract

In this paper, we address a novel simulated annealing(SA)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip(SoCs), on the assumption that the test platform proposed in [1] is installed. The proposed method efficiently mixed the rectangle packing method with SA and improved the scheduling results by locally changing the test access mechanism(TAM) widths for cores and the testing orders. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce the overall test time.

본 논문에서는 NoC 기반 SoC의 테스트 시간을 감소시키기 위하여 NoC를 TAM으로 재활용하는 구조를 바탕으로 하는 새로운 형태의 스케줄링 알고리즘을 제안한다. 제안한 방식에서는 기존 연구된 NoC 테스트 플랫폼을 사용하여 스케줄링 문제를 rectangle packing 문제로 변환하고 이를 simulated annealing(SA) 기법을 적용하여 향상된 스케줄링 결과를 유도한다. ITC'02 벤치회로를 이용한 실험 결과 제안한 방법이 기존 방법에 비해 최대 2.8%까지 테스트 시간을 줄일 수 있음을 확인하였다.

Keywords

References

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