The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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Estimation Technique for Additional Delay Time due to Interconnection Branches in Source-Termination Scheme

Source-Termination 구조에서 연결선 분기로 인한 추가 지연 시간 예측 기법

  • Published : 2008.04.01
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Abstract

In this paper, we propose a simple numerical formula which can estimate the additional delay time due to interconnection branches in general source-termination scheme. We show that interconnection branches have influence on both signal quality and time delay. Using the proposed numerical formula, time delay can be easily predicted by system designers.

Keywords

References

  1. Brian Young, "Digital Signal Integrity Modeling and Simulation with Interconnects and Packages," Prentice-Hall, 2000, Ch. 2
  2. Sephen H. Hall, Garrett W. Hall, James A. McCall, "High-Speed Digital System Design," John Wiley & Sons, 2000, Ch. 3
  3. Green L., "Understanding the importance of signal integrity," Circuits and Devices Magazine, IEEE Volume 15, Issue 6, Nov. 1999
  4. Schuster C., Fichtner W., "Parasitic modes on printed circuit boards and their effects on EMC and signal integrity," Electromagnetic Compatibility, IEEE Transactions on Volume 43, Issue 4, Nov. 2001
  5. Pitica D., Lungu S., Pop O., "Signal integrity face to face with EMC in PCB design," Electronics Technology: Integrated Management of Electronic Materials Production, 2003
  6. Eric Bogatin, "Signal Integrity - Simplified," Prentice-Hall, 2004, Ch. 7
  7. Stephen H. Hall, Garrett W. Hall, James A. McCall, "High-speed Digital System Design- A Handbook of Interconnection Theory and Design Practices", Wilel & Sons, Inc., Ch. 2
  8. Attilio J. Rainal, "Transmission Properties of Balanced Interconnections", IEEE Trans, Vol.16, pp.137-145, Feb. 1993
  9. Synopsys, http://www.synopsys.com/