The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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The Design of 1.2V $3^{rd}$ Order 4bit Sigma Delta Modulator with Improved Operating Time of High Speed DWA

고속 DWA의 동작시간을 개선한 1.2V $3^{rd}$ 4bit 시그마 델타 변조기 설계

  • 이순재 (전북대학 전자정보공학부) ;
  • 김선홍 (전북대학 전기공학과) ;
  • 조성익 (전북대학 전자정보공학부)
  • Published : 2008.06.01
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Abstract

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

Keywords

References

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