대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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2 레벨 탐색을 이용한 스피어 디코딩 알고리즘과 VLSI 구현

Sphere Decoding Algorithm and VLSI Implementation Using Two-Level Search

  • 현트롱안 (경희대학교 전자.전파공학과) ;
  • 조종민 (경희대학교 전자.전파공학과) ;
  • 김진상 (경희대학교 전자.전파공학과) ;
  • 조원경 (경희대학교 전자.전파공학과)
  • Huynh, Tronganh (Department of Electronics and Radio Engineering, KyungHee University) ;
  • Cho, Jong-Min (Department of Electronics and Radio Engineering, KyungHee University) ;
  • Kim, Jin-Sang (Department of Electronics and Radio Engineering, KyungHee University) ;
  • Cho, Won-Kyung (Department of Electronics and Radio Engineering, KyungHee University)
  • 발행 : 2008.06.25
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초록

본 논문에서는 새로운 2레벨 탐색 스피어 디코딩 알고리즘과 그 하드웨어 구조를 제안한다. 제안된 알고리즘은 심볼검출 시에 성능향상에 영향을 줄 수 있는 유용한 후보군이 이전 단계에서 버려지는 것을 피하기 위해서, 2 레벨 트리탐색을 동시에 수행한다. 시뮬레이션 결과, 제안된 알고리즘이 BER 측면에서 기존의 알고리즘보다 성능이 우수함을 확인할 수 있었다. 제안된 하드웨어 구조는 낮은 복잡도와 고정된 throughput을 갖는 구조로써 BPSK, QPSK, 16-QAM, 64-QAM의 변조방식을 지원한다. 하드웨어 측면에서 큰 복잡도를 갖는 정렬 블럭은 다른 블럭과 하드웨어를 공유함으로써 면적을 감소시켰고, 제안된 하드웨어 구조는 기존의 구조들과 비교했을 때 면적이 감소되고 성능이 향상됨을 확인하였다.

In this paper, a novel 2-level-search sphere decoding algorithm for multiple-input multiple-output (MIMO) detection and its VLSI implementation are presented. The proposed algorithm extends the search space by concurrently performing symbol detection on 2 level of the tree search. Therefore, the possibility of discarding good candidates can be avoided. Simulation results demonstrate the good performance of the proposed algorithm in terms of bit-error-rate (BER). From the proposed algorithm, an efficient very large scale integration (VLSI) architecture which incorporates low-complexity and fixed throughput features is proposed. The proposed architecture supports many modulation techniques such as BPSK, QPSK, 16-QAM and 64-QAM. The sorting block, which occupies a large portion of hardware utilization, is shared for different operating modes to reduce the area. The proposed hardware implementation results show the improvement in terms of area and BER performance compared with existing architectures.

키워드

참고문헌

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