Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지

A System Level Network-on-chip Model with MLDesigner

  • Agarwal, Ankur (Dept. of Computer Science and Engineering, Florida Atlantic University) ;
  • Shankar, Rabi (Dept. of Computer Science and Engineering, Florida Atlantic University) ;
  • Pandya, A.S. (Dept. of Computer Science and Engineering, Florida Atlantic University) ;
  • Lho, Young-Uhg (Dept. of Computer Education, Silla University)
  • Published : 2008.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

Keywords

References

  1. G. Desoli, E. Filippi, "An Outlook on the Evolution of Mobile Terminals: From Monolithic to modular multi-radio, multi-application platforms", IEEE magazine on Circuits and Systems, vol. 6, No. 2, pp. 17-29, 2006 https://doi.org/10.1109/MCAS.2006.1648987
  2. L. Benini and G. De Micheli. Networks on chip: a new SOC paradigm, IEEE Computer, vol. 35 No. 1, pp.70-78, 2002
  3. J. Ahmed Meine, Wolf Wayne, Multiprocessor System-On-Chips. Morgan Kaufamann Publisher, 2005
  4. A. Agarwal, R. Shankar, "A Layered Architecture for NOC Design methodology", IASTED Conference on parallel and Distributed Computing and Systems, pp. 659-666, 2005
  5. A. Hemani, A. Jantsch, S. Kumar A. Postula, J. Öberg, M. Millberg, D. Lindqvist, Network on Chip: an architecture for billion transistor era, Proc. of IEEE NorChip Conference, pp. 8-12, November 2000
  6. D. Bertozzi and L. Benini, "Xpipes: A network-on-chip architecture for gigascale system-on-chip," IEEE Circuits and Systems., vol. 4, no.1 pp. 18-31, 2004 https://doi.org/10.1109/MCAS.2004.1330747
  7. A. Jantsch and H. Tenhunen. Networks on Chip (Kluwer Academic Publisher, 2003
  8. D. Kim, M. Kim, G.E. Sobelman, "CDMA-based network-on-chip architecture", IEEE Asia-Pasific Conference on Circuits and Systems, vol. 1, pp. 137-140, December 2004
  9. A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, C.A. Zeferino, C.A., "SPIN: a scalable, packet switched, on-chip micro-network, IEEE Conference and exhibition on, Design, Automation and Test in Europe, pp. 70-72, 2003
  10. P. Pratim Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures", IEEE transactions on Computers, vol. 54, Issue 8, pp. 1025-1040, Aug. 2005 https://doi.org/10.1109/TC.2005.134
  11. P. Bhojwani, R. Mahapatra, Jung Kim Eun, T. Chen, "A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systems", IEEE International Conference on VLDI Design, pp.124-129, 2005
  12. D. Rostilav, V. Vishnyakov, E. Friedman, R. Ginosar, An asynchronous router for multiple service levels networks on chip, 11th IEEE international symposium on asynchronous circuits and systems, pp.44-53, March 2005
  13. A. Siebenborn, O. Bringmann, W. Rosenstiel, "Communication analysis for network-on-chip design", IEEE International conference on Parallel Computing in Electrical Engineering, oo. 315-320, Sepetmber 2004
  14. J. Hu, R. Marculescu, "Energy-aware Communication and task scheduling for network-on-chip architectures under real-time constraints", IEEE Conference on Design, Automation and Test, vol. 1, pp. 234-239, Febrary 2004
  15. J. Madsen, S. Mahadevan, K. Virk, M. Gonzalez, "Network-on-chip modeling for system-level multiprocessor simulation", IEEE 14th Conference on Real Time System, pp. 265-274, 2003
  16. P.T. Wolkotte, G.J.M. Smit, G.K. Rauwerda, L.T. Smit, "An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip", 19th IEEE International Conference on Parallel and distributed Processing, pp. 155-163, 2005
  17. W. J. Dally, B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks", IEEE Conference on Design and Automation, pp. 684-689, June 2001
  18. C. Albenes Zeferino Frederico G. M. E. Santo, Altarniro Amadeu Susin, "ParlS: A Parameterizable Interconnect Switch for Networks-on-Chips", ACM Conference, pp. 204-209, 2004
  19. T. Bjerregaard, J. Sparso, "Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip", IEEE Proceedings on Norchip Conference, pp. 269 - 272, November 2004
  20. A. Barger, D. Goren, A. Kolodny, "Design and modelling of network on chip interconnects using transmission lines", 11th IEEE International Conference on Electronics, Circuits and Systems, pp. 403-406, December 2004
  21. A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar, "Comparative analysis of serial vs parallel links in NoC", IEEE International Proceedings on System-on-Chip, pp. 185-188, November 2004
  22. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS architecture and design process for network on chip", Journal of Systems Architecture, December 2003
  23. D. Bertozzi, L. Benini, G. De Micheli, "Error control schemes for on-chip communication links: the energy-reliability tradeoff", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, Issue 6, pp. 818-831, June 2005 https://doi.org/10.1109/TCAD.2005.847907
  24. S. J. Lee, K. Lee, S.J. Song, H.J. Yoo, "Packet-switched on-chip interconnection network for system-on-chip applications", IEEE Transaction on Circuits and Systems II, vol. 52, Issue 6, pp. 308-312, June 2005 https://doi.org/10.1109/TCSII.2005.848972