The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

Design of High Speed Encryption/Decryption Hardware for Block Cipher ARIA

블록 암호 ARIA를 위한 고속 암호기/복호기 설계

  • 하성주 (인하대 공대 정보통신공학과) ;
  • 이종호 (인하대 공대 정보통신공학과)
  • Published : 2008.09.01
Download PDF
⟨ Previous Next ⟩

Abstract

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

Keywords

References

  1. 임용진, 홍진, 지성택, "스트림 암호의 발전 방향" 한국정보과학회, 정보과학회지 제23권 제1호, pp. 40-45, 2005. 1
  2. http://www.nsri.re.kr/kor/aria.html
  3. Daesung Kwon, Jaesung Kim, Sangwoo Park et al. "New block cipher: ARIA", In Proc. Information Security and Cryptology (ICISC'03), Seoul, Korea, LNCS 2971, Springer-Verlag, pp. 432-445, November 27-28, 2003
  4. 장환석, 이호정, 구본욱, 송정환, "64비트 마이크로프로 세서에 적합한 블록암호 ARIA 구현방안", 한국정보보호학회, 정보보호학회지 제16권 제3호, pp. 63-74, 2006. 6
  5. 박진섭, 윤연상, 김용대, 양상운, 장태주, 유영갑, "ARIA 암호 알고리즘의 하드웨어 설계 및 구현", 대한전자공학회, 전자공학회논문지 제42권 SD편 제4호, pp. 29-36, 2005. 4.
  6. Jinsub Park, Young-Dae Kim, Sangwoon Yang, Younggap You, "Low power compact design of ARIA block cipher", Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, May 2006
  7. S. Yang, J. Park, and Y. You, "The smallest ARIA module with 16-bit architecture", ICISC 2006, LNCS 4296, pp. 107-117 , 2006
  8. 유권호, 구본석, 양상운, 장태주, "경량화된 확산계층을 이용한 32-비트 구조의 소형 ARIA 연산기 구현", 한국정보보호학회, 정보보호학회논문지 제16권 제6호, pp. 15-24, 2006. 12
  9. Yeong-Jae Oh, Hanho Lee, Chong-Ho Lee, "Dynamic Partial Reconfigurable FIR Filter Design," Reconfigurbale Computing: Architectures and Applications (ARC 2006), LNCS3985, Mar. 2006. (SCIE)
  10. Chang-Seok Choi and Hanho Lee, "A Self- Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform," IEICE Transactions on Information and Systems, vol. E90-D, no. 12, pp. 1932-1938, Dec. 1. 2007. (SCIE) https://doi.org/10.1093/ietisy/e90-d.12.1932
  11. NSRI: ARIA Algorithm Specification, http://www.nsri.re.kr/ARIA/doc/ARIA-specification.pd f, 2004 (in Korea)
  12. Bonseok Koo, Gwonho Ryu, Taejoo Chang, Sangjin Lee, "Design and Implementation of Unified Hardware for 128-Bit Block Ciphers ARIA and AES", 한국전자통신연구원, ETRI Journal 제29권 제6 호, 2007. 12
  13. D. Kotturi, S.M. Yoo, and J. Blizzard, "AES Crypto Chip Utilizing High-Speed Parallel Pipelined Architecture," IEEE Int'l Symp. on Circuits and Systems(ISCAS-05), Kobe, Japan, pp.4653-4656, May 2005
  14. A. Hodjat, I. Verbauwhede, A 21.54 Gbits/s fully pipelined AES processor on FPGA, in: IEEE Symposium on Field-Programmable Custom Computing Machines, 2004
  15. Yongzhi Fu, Lin Hao, Xuejie Zhang and Rujin Yang, "Design of an extremely high performance counter mode AES reconfigurable processor", Embedded Software and Systems, 2005. Second International Conference on Embedded Software and Systems(ICESS'05), 16-18 Dec. 2005
  16. George Mason University, Hardware IP Cores of Advanced Encryption Standard AES Rijndael, http://ece.gmu.edu/crytpo/rijndael.htm
  17. M.R.M. Rizk, M. Morsy, "Optimized Area and Optimized Speed Hardware Implementatoins of AES on FPGA" International Design and Test Workshop, 2007 2nd, pp. 207-217, 16-18 Dec. 2007