Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)
- Volume 15 Issue 3
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- Pages.47-52
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- 2008
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- 1226-9360(pISSN)
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- 2287-7525(eISSN)
The Film Property and Deposition Process of TSV Inside for 3D Interconnection
3D Interconnection을 위한 실리콘 관통 전극 내부의 절연막 증착 공정과 그 막의 특성에 관한 연구
- Seo, Sang-Woon (Department of Electronic Engineering, Kangnam University) ;
- Kim, Gu-Sung (Department of Electronic Engineering, Kangnam University)
- Published : 2008.09.30
Abstract
This investigation was performed in order to study the properties of deposition and layers by Silicon Dioxide, SiO2, as dielectric onto Via and Trench which have high Aspect Ratio (AR). Thus, in order to confirm these properties, three types of CVD, which were PECVD, PETEOS, and ALD, were selected. On the experiment each of the property sections was estimated that step overage of PECVD: <30%, PETEOS: 45%, ALD: 75% and the RSM of PECVD: 27.8 nm, PETEOS: 2.1 nm, ALD: <2.0 nm. As a result of this experiment for the property of electric film, ALD was valuated to be the most favorable outcome. However, ALD was valuated to have the least quality for the deposition rate. ALD deposition rate,
높은 종횡비를 갖는 비아 및 트렌치 상에 절연 막으로서