JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of a Latchup-Free ESD Power Clamp for Smart Power ICs

  • Park, Jae-Young (Department of Electronics and Computer Engineering, Hanyang University) ;
  • Kim, Dong-Jun (Department of Electronics and Computer Engineering, Hanyang University) ;
  • Park, Sang-Gyu (Department of Electronics and Computer Engineering, Hanyang University)
  • Published : 2008.09.30
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Abstract

A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a $0.35{\mu}m$ 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.

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References

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