고속 LVDS 응용을 위한 전송선 분석 및 설계 최적화

Analysis and Design Optimization of Interconnects for High-Speed LVDS Applications

  • 류지열 (부경대학교 전자컴퓨터통신공학부) ;
  • 노석호 (안동대학교 전자공학과)
  • Ryu, Jee-Youl (Division of Electronic, Computer and Telecommunication Engineering Pukyong National University) ;
  • Noh, Seok-Ho (Electronic Engineering, College of Electronic & Information Engineering, Andong National University)
  • 투고 : 2009.07.27
  • 발행 : 2009.10.25

초록

본 논문에서는 고속 저전압 차동 신호(Low-Voltage Differential Signaling, LVDS) 전송방식의 응용을 위한 전송선 분석 및 설계 최적화 방법을 제안한다. 차동 전송 경로 및 저전압 스윙 방법의 발전으로 인해 저전압 차동 신호 전송방식은 데이터 통신 분야, 고 해상도 디스플레이 분야, 평판 디스플레이 분야에서 매우 적은 소비전력, 개선된 잡음 특성 및 고속 데이터 전송률을 제공한다. 본 논문은 차동 유연성 인쇄 회로 보드(flexible printed circuit board, FPCB) 전송선에서 선 폭, 선 두께 및 선간격과 같은 전송선 설계 변수들의 최적화 기법을 이용하여 직렬 접속된 전송선에서 발생하는 임피던스 부정합과 신호 왜곡을 감소시키기 위해 개선 모델과 개발된 수식을 제안한다. 이러한 차동 FPCB 전송선의 고주파 특성을 평가하기 위해 주파수 영역에서 전파(full-wave) 전자기 시뮬레이션 및 시간 영역 시뮬레이션을 각각 수행하였다. 본 논문에서 제안하는 방법은 저전압 차동 신호 방식의 응용을 위한 고속 차동 FPCB 전송선을 최적화하는데 매우 도움이 되리라 믿는다.

This paper addresses the analysis and the design optimization of differential interconnects for high-speed Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, and time-domain transient simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

키워드

참고문헌

  1. J. Y. Ryu and S. H. Noh, 'Analysis and Design Optimization of Interconnects for High-Speed LVDS Applications,' Conference of the Korean Institute of Maritime Information & Communication Science, Vol. 11, No. 2, pp.761-764, October 2007
  2. D. Chowdhury et. al., 'Analysis of differential termination technique in cascading of high-speed LVDS signals on a PCB,' Procs. of the IEEE INDICON First India Annual Conference, pp.557-560, Dec. 2004
  3. X. Fan et. al., ' The performance improvement of via structure in LVDS by optimizing partial widths of the traces,' Procs. of ICMMT 4th International Conference on Microwave and Millimeter Wave Technology, pp. 398 401, Aug. 2004
  4. S. Ahn et. al., 'Solution space analysis of interconnects for low voltage differential signaling (LVDS) applications,' Electrical Performance of Electronic Packaging, pp. 327 330, Oct. 2001
  5. M. M. Mechaik, 'An evaluation of single ended and differential impedance in PCBs,' International Symposium on Quality Electronic Design, pp. 301 306, Mar. 2001
  6. E. Recht and S. Shiran, 'A simple model for characteristic impedance of wide microstrip lines for flexible PCB,' IEEE International Symposium on Electromagnetic Compatibility, pp. 1010 1014, Aug. 2002
  7. IEEE standard for Low Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), IEEE Std 1596.3 1996, July 1996
  8. National Semiconductor, Application Note 1085, June 1999
  9. J. Y. Lee et. al., 'A 400Mbps/ch SiDP receiver for mobile TFT LCD driver IC,' SID 06, pp.1499 1501, June 2006
  10. J. Goldie, 'LVDS goes the distance,' SID 99, pp.1 4, June 1999
  11. H. W. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall PTR, New Jersey, p. 186 221
  12. http://focus.ti.com/lit/ug/sllu039/sllu039.pdf