JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low-Power Bus Architecture Composition for AMBA AXI

  • Na, Sang-Kwon (Dep. EE., Korea Advanced Institutc of Science and Technology) ;
  • Yang, Sung (Systcm LSI Division of Samsung electronics) ;
  • Kyung, Chong-Min (Dep. EE., Korea Advanced Institutc of Science and Technology)
  • Published : 2009.06.30
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Abstract

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

Keywords

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