Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

High-Speed Low-Complexity Two-Bit Level Pipelined Viterbi Decoder for UWB Systems

UWB시스템을 위한 고속 저복잡도 2-비트 레벨 파이프라인 비터비 복호기 설계

  • Goo, Yong-Je (School of Information and Communication Engineering, Inha University) ;
  • Lee, Han-Ho (School of Information and Communication Engineering, Inha University)
  • 구용제 (인하대학교 정보통신공학부) ;
  • 이한호 (인하대학교 정보통신공학부)
  • Published : 2009.08.25
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.

본 논문에서는 MB-OFDM 초광대역 시스템을 위한 높은 속도와 저복잡도를 갖는 2-비트 레벨 파이프라인 비터비 디코더를 소개한다. 가산-비교-선택 유닛(ACSU)은 비터비 복호기의 주요 병목지점으로서, 임계경로를 줄이는 2-step look-ahead 기법에 기반을 둔 2-비트 레벨 파이프라인 MSB-first ACSU 유닛에 대해 제안한다. 제안하는 ACSU 구조는 1.8V의 공급 전압에서 동작하는 $0.18-{\mu}m$ CMOS 공정을 이용하여 구현하였다. ACSU유닛은 870MHz의 클록 주파수에서 동작하며, 1.7Gb/s 의 데이터 처리율을 가진다.

Keywords

References

  1. Time Domain, 'UWB Applications, Demonstration & Regulatory Update,' Sept 2001 workshop, March 20, 2001
  2. A. Batra et al., 'Multi-band OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a,' IEEE P802.15-03/268r3, March 2004
  3. A. Batra, J. Balakrishnan, G. R. Aiello, J. R. Foerster, A. Dabak, 'Design of Multiband OFDM System for Realistic UWB Channel Environment,' IEEE Trans. on Microwave Theory and Techniques 52 (2004) 2123-2138 https://doi.org/10.1109/TMTT.2004.834184
  4. A. J. Viterbi, 'Error bounds for convolutional coding and an asymptotically optimum decoding algorithm,' IEEE Trans. Information Theory IT-13 (1967) 260-269
  5. P. J. Black and T. H. Meng, 'A 140-Mb/s, 32-state, radix-4 Viterbi decoder,' IEEE Journal of Solid-State Circuits 27 (1992) 1877-1885 https://doi.org/10.1109/4.173118
  6. G. Feygin, and P. G. Gulak, 'Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi decoders,' IEEE Trans. Commun 41 (1993) 425-429 https://doi.org/10.1109/26.221067
  7. D. Dabiri, and I.F Blake 'An Area Efficient Surviving Paths U it for the Viterbi Algorithm,' IEEE Trans. Commun. 1 (1999) 300-304 https://doi.org/10.1109/ICC.1999.767949
  8. Y. Gang, A. T. Erdogan, and T. Arslan, 'An efficient pre-tracback approach for Viterbi decoder Targeting Wireless Communication Applications' IEEE Transaction on Circuits and Systems 53 (2007)1918-1927 https://doi.org/10.1109/TCSI.2006.881187
  9. J. A. Heller, I. M. Jacobs, 'Viterbi decoding for satellite and space communication,' IEEE Trans. Commun. Technol 19 (1971) 835-848 https://doi.org/10.1109/TCOM.1971.1090711
  10. A. P. Hekstra, 'An alternative to metric rescaling in Viterbi decoders,' IEEE Trans. Commun. 37 (1989) 1220-1222 https://doi.org/10.1109/26.46516
  11. G. Feygin, and P. G. Gulak, 'Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi decoders,' IEEE Trans. Commun 51 (1993) 425-429 https://doi.org/10.1109/26.221067
  12. D. Dabiri, and I.F Blake 'An Area Efficient Surviving Paths Unit for the Viterbi Algorithrn,' IEEE Trans. Commun. 1 (1999) 300-304 https://doi.org/10.1109/ICC.1999.767949
  13. Y. Gang, A. T. Erdogan, and T. Arslan, 'An eficient pre-tracback approach for Viterbi decoder Targeting Wireless Communication Applications' IEEE Transaction on Circuits and Systems 53 (2007) 1918-1927 https://doi.org/10.1109/TCSI.2006.881187