ETRI Journal

  • 제31권6호
  • /
  • Pages.795-802
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  • 2009
  • /
  • 1225-6463(pISSN)
  • /
  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
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Design of AT-DMB Baseband Receiver SoC

  • Lee, Joo-Hyun (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Kim, Hyuk (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Kim, Jin-Kyu (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Koo, Bon-Tae (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Eum, Nak-Woong (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Lee, Hyuck-Jae (Electrical Engineering Department, KAIST)
  • 투고 : 2009.04.27
  • 심사 : 2009.08.06
  • 발행 : 2009.12.31
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초록

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT-DMB baseband receiver SoC is fabricated using 0.13 ${\mu}m$ technology and shows successful operation with a 50 mW power dissipation.

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참고문헌

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