Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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FPGA Implementation of Scan Conversion Unit using SIMD Architecture and Hierarchical Tile-based Traversing Method

계층적 타일기반 탐색기법과 SIMD 구조가 적용된 스캔변환회로의 FPGA 구현

  • 하창수 (동의대학교 컴퓨터공학과) ;
  • 최병윤 (동의대학교 컴퓨터공학과)
  • Received : 2010.05.15
  • Accepted : 2010.06.24
  • Published : 2010.09.30
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Abstract

In this paper, we present research results of developing high performance scan conversion unit and implementing it on FPGA chip. To increase performance of scan conversion unit, we propose an architecture of scan converter that is a SIMD architecture and uses tile-based traversing method. The proposed scan conversion unit can operate about 124Mhz clock frequency on Xilinx Vertex4 LX100 device. To verify the scan conversion unit, we also develop shader unit, texture mapping unit and $240{\times}320$ color TFT-LCD controller to display outputs of the scan conversion unit on TFT-LCD. Because the scan conversion unit implemented on FPGA has 311Mpixels/sec pixel rate, it is applicable to desktop pc's 3d graphics system as well as mobile 3d graphics system needing high pixel rates.

본 논문에서는 3차원 그래픽스 시스템에 적용 가능한 고성능 스캔변환회로를 설계하고 FPGA로 구현한 내용을 기술한다. 스캔변환회로의 성능을 높이기 위하여 본 논문에서는 계층적 타일기반 탐색기법과 SIMD 구조를 적용한 스캔변환회로 구조를 제안한다. 제안한 스캔변환회로는 Xilinx Vertex4 LX100 FPGA 디바이스에서 약 124Mhz로 동작가능하며, 실제 연산결과의 올바른 출력을 확인하기 위해 셰이더, 텍스처 매핑회로 그리고 $240{\times}320$ 컬러 TFT-LCD의 컨트롤러를 설계하여 통합하였다. FPGA상에 구현된 스캔변환회로는 약 311Mpixels/sec의 픽셀 생성율을 가지므로 데스크 탑 PC용 3차원 그래픽스 시스템뿐만 아니라 고성능을 요구하는 모바일 3차원 그래픽스 시스템에도 적용 가능하다.

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References

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