JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A TX Clock Timing Technique for the CIJ Compensation of Coupled Microstrip Lines

  • Jung, Hae-Kang (Dept. of Electronic and Electrical Engineering Pohang University of Science and Technology (POSTECH)) ;
  • Lee, Soo-Min (Dept. of Electronic and Electrical Engineering Pohang University of Science and Technology (POSTECH)) ;
  • Sim, Jae-Yoon (Dept. of Electronic and Electrical Engineering Pohang University of Science and Technology (POSTECH)) ;
  • Park, Hong-June (Dept. of Electronic and Electrical Engineering Pohang University of Science and Technology (POSTECH))
  • Received : 2010.08.19
  • Accepted : 2010.09.27
  • Published : 2010.09.30
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Abstract

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a $0.18\;{\mu}m$ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.

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References

  1. K. Lee, et al., “A Serpentine Guard Trace to Reduce the Far-End Crosstalk Voltage and the Crosstalk Induced Timing of Parallel Microstrip Lines,” IEEE Transactions on Advanced Packaging, Vol.31, No.4, pp.809-817, Nov., 2008. https://doi.org/10.1109/TADVP.2008.924226
  2. K. Lee, et al., “Serpentine Guard Trace to Reduce Far-end Crosstalk and Even-Odd Mode Velocity Mismatch of Microstrip Lines by More than 40%,” ECTC, 2007, pp.329-332.
  3. K. Lee, et al., “Serpentine Microstrip Lines with Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces,” IEEE Transactions on Advanced Packaging, Vol.33, No.3, pp.552-558, May, 2010. https://doi.org/10.1109/TADVP.2009.2033938
  4. S.K. Lee, et al., “FEXT-eliminated stub-alternated microstrip line for multi-gigabit/second parallel links,” Electronics Letters, Vol.44, No.4, Feb., 2008, pp.272-273. https://doi.org/10.1049/el:20083043
  5. D.G. Kam, et al., “A New Twisted Differential Line Structure on High-Speed Printed Circuit Boards to Enhance Immunity to Crosstalk and External Noise,” IEEE Microwave and Wireless Components Letters, Vol.13, No.9, Sep., 2003. https://doi.org/10.1109/LMWC.2003.815181
  6. H.K. Jung, et al., “A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control,” IEEE Journal of Solid State Circuits, Vol.44, No.11, pp.2891-2900, Nov., 2009. https://doi.org/10.1109/JSSC.2009.2028917
  7. J. F. Buckwalter, et al., “Cancellation of Crosstalk-Induced Jitter,” IEEE Journal of Solid State Circuits, Vol.41, No.3, Mar., 2006, pp.621-632. https://doi.org/10.1109/JSSC.2005.864113
  8. K-I. Oh, et al., “A 5-Gb/s/pin Transceiver for DDR Memory Interface with a Crosstalk Suppression Scheme,” IEEE J. Solid-State Circuits, Vol.44, No.8, pp.2222-2232, Aug., 2009. https://doi.org/10.1109/JSSC.2009.2022303

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