JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Simulation and Modelling of the Write/Erase Kinetics and the Retention Time of Single Electron Memory at Room Temperature

  • Boubaker, Aimen (Departement d'electronique Institut des Nanotechnologies de Lyon-INL, INSA-Lyon) ;
  • Sghaier, Nabil (Departement des sciences physiques, Faculte des Sciences de Monastir) ;
  • Souifi, Abdelkader (Departement d'electronique Institut des Nanotechnologies de Lyon-INL, INSA-Lyon) ;
  • Kalboussi, Adel (Departement des sciences physiques, Faculte des Sciences de Monastir)
  • Received : 2009.11.06
  • Published : 2010.06.30
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Abstract

In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.

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References

  1. V. Ray, R. Subramanian, P. Bhadrachalam, L. C. Ma, C. U. Kim and S.J. Koh “VCMOS-compatible fabrication of room temperature single-electron devices,” Nature Nanotechnology, Sep. 2008.
  2. C. Wasshuber, H. Kosina, and S. Selberherr. “SIMON - A simulator for single-electron tunnel devices and circuits,” IEEE Trans. Comp. Aided Design Integr. Circ. Sys., 16(9), p937, 1997. https://doi.org/10.1109/43.658562
  3. K. Likharev and A. Korotkov, “Toward practical digital single electronics,” Electrochm. Soc. Meeting Abstr., vol. 96-2, Oct 1996, p. 563.
  4. Christoph Wasshuber, “A Comparative Study of Single-Electron Memories,” IEEE Transactions on electron devices, Vol. 45, No 11, 1998, pp 2365-2371. https://doi.org/10.1109/16.726659
  5. K. Nakazato and H. Ahmed, “The multiple-tunnel junction and its application to single-electron memory and logic circuits,” Jpn. J. Appl Phys., vol. 34, Feb. 1995, pp. 700-706. https://doi.org/10.1143/JJAP.34.700
  6. C.Wasshuber, “ Computational Single-Electronics,” SpringerWienNewyork, 2001, pp 169-176.
  7. C.Dubuc, J. Beauvais, and D. Drouin, “Single electron transistors with wide operating temperature rang,” Applied Physics Letters 90, 2007, 113104. https://doi.org/10.1063/1.2713171
  8. A. Boubaker et al, “Electrical characteristics and modelling of multi-island single-electron transistor using SIMON simulator,” Microelectronics Journal, 2008, pp 543-546.
  9. MAPLE 6, Waterloo Maple Inc, Available: http://www.maplesoft.com
  10. M.Hocevar, “ Croissance et caracterisation electrique de nanocristaux d’InAs/$SiO_2$ pour des applications de memoires non volatiles sur silicium”, thesis INL, Oct 2008.
  11. J.W. Yoon et al., “Dispersion of nanosized noble metals in $TiO_2$ matrix and their photoelectrode properties,” Thin Solid Films 483, 2005, pp 276-282. https://doi.org/10.1016/j.tsf.2005.01.006
  12. http://sites.google.com/site/selfreliantenergy/Home/physics/workfunction, 2009.
  13. T.G. Lei et al, “Effect of microstructure of $TiO_2$ thin films on optical band gap energy,” Chin. Phys.Lett, Vol. 22, No. 7, 2005, p787. https://doi.org/10.1088/0256-307X/22/4/002

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