Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Improving Symbolic Model Checking Performance Withy Retiming

Retiming을 이용한 Symbolic Model Checking 성능 향상에 관한 연구

  • Received : 2010.08.06
  • Accepted : 2010.08.19
  • Published : 2010.10.30
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Abstract

This paper presents an application of retiming to model checking, a branch of formal verification. Retiming can change the transition relation of a circuit without changing its input-output behaviour by relocating its registers. With the retiming, a given circuit can have a different structure more adequate for model checking. This paper proposes a cost function to reflect the number of registers and the characteristic of its transition relation and develops a heuristic annealing algorithm to search efficiently the circuit structures obtained by retiming. Experimental results show that the proposed method can improve the model checking performance.

이 논문에서는 형식 검증(formal verification)의 한 분야인 모델 검증(model checking)에 재타이밍(retiming) 기법을 적용하는 방법에서 대해 연구하였다. 재타이밍은 주어진 회로의 레지스터들을 재배치함으로써, 입출력 동작을 바꾸지 않으면서 전이 관계(transition relation)을 변환할 수 있는 기법이다. 이러한 재타이밍을 이용하면 모델 검증을 더 효율적으로 수행하도록 회로를 바꿀 수 있다. 이 논문에서는, 레지스터의 개수와 전이 관계의 특성을 반영한 cost 함수를 제안하고, 재타이밍으로 얻을 수 있는 회로 구조들을 효율적으로 탐색하는 heuristic annealing 알고리즘을 개발한다. 제안된 방법이 모델 검증의 성능을 향상시킬 수 있음을 실험 결과를 통해 보여주었다.

Keywords

References

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