The Transactions of The Korean Institute of Electrical Engineers (전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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A 12-bit 1MS/s SAR ADC with Rail-to-Rail Input Range

Rail-to-Rail의 입력 신호 범위를 가지는 12-bit 1MS/s 축차비교형 아날로그-디지털 변환기

  • 김두연 (고려대학교 마이크로/나노협동과정) ;
  • 정재진 (고려대학교 전기전파공학과) ;
  • 임신일 (서경대학교 컴퓨터공학과) ;
  • 김석기 (고려대학교 전기전자전파공학부)
  • Published : 2010.02.01
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Abstract

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

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References

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