DOI QR코드

DOI QR Code

부 스큐 지연 방식과 피드포워드 방식을 사용한 링 발진기의 대신호 해석

A Large-Signal Analysis of a Ring Oscillator with Feed-Forward and Negative Skewed Delay

  • 이정광 (전북대학 전자정보공학부) ;
  • 이순재 (전북대학 전자정보공학부) ;
  • 정항근 (전북대학 전자공학부)
  • 투고 : 2009.12.15
  • 심사 : 2010.06.25
  • 발행 : 2010.07.01

초록

This paper presents a large signal analysis of ring-type oscillators with feed forward and negative skewed delay scheme. The analysis yields the frequency increase factor due to two schemes. The large signal analysis is needed, because small signal model is limited to the initial stage of oscillation[1]. For verification of the frequency increase factor, simulation were done under the same conditions for the two different types of ring oscillators, i.e., with and without feed forward and negative skewed delay scheme. Simulation results are in good agreement with predictions based on analysis.

키워드

참고문헌

  1. B. Razavi, Design of Analog CMOS Integrated Circuits, pp. 484-495, McGraw-Hill, 2001.
  2. De Muer, Borremans, Steyaert, and Li Puma, "A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise up conversion minimization" IEEE J. Solid-State Circuits, vol. 35 no. 7, Jul. 2000.
  3. A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998. https://doi.org/10.1109/4.658619
  4. Yalcin Alper Eken and John P. Uyemura, "A 5.9-GHz voltage-controlled ring oscillator in $0.18-{\mu}m$ CMOS" IEEE J. Solid-State Circuits, vol. 39 no. 1, Jan. 2004.
  5. Seog-Jun Lee, Beomsup Kim, and Kwyro Lee, "A Novel High-Speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed delay Scheme" IEEE J. Solid-State Circuits, Vol. 32. NO.2, Feb. 1997.
  6. F. H. Gebara, J. D. Schaub, a. J. Drake, K.J. Nowka, R. B. Brown, "4.0Ghz 0.18um CMOS PLL based on an interpolative oscillator", Symp. on VLSI Circuits 2005, pp. 100-103, Jun. 2005.
  7. 김성하, 김삼동, 황인석, "향상된 부 스큐 고속 VCO를 이용한 초고주파 PLL," 대한전자공학회 SC편, vol. 42, pp. 315-327, Jun. 2005.
  8. Ge Yan, Chen Zhongjian, and Jl Lijiu, "Design of CMOS high speed self-regulating VCO using negative skewed delay scheme," Proc. of ICSICT, pp. 1333-1336, Feb. 2004.
  9. Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, pp. 196-233, McGraw-Hill, 1999.
  10. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits, pp. 179-234, Prentice Hall, 1995.
  11. Tim Grotjohn, Bernd Hoefflinger, "A parametric short-channel MOS transistor model for subthreshold and strong inversion current" IEEE J. Solid-state Circuits, vol. 31 no. 2, Jun. 1984.