대한전자공학회논문지TC (Journal of the Institute of Electronics Engineers of Korea TC)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

무선 네트웤 라우터응용을 위한 고성능32비트 내장AES

High Performance 32-bit Embedded AES for Wireless Network Router Applications

  • 등린 (충북대학교 정보통신공학과) ;
  • 유영갑 (충북대학교 정자정보대학)
  • Lin, Deng (School of Information and Communication Engineering, Chungbuk National University) ;
  • You, Young-Gap (College of Electrical and Computer Engineering, Chungbuk National University)
  • 투고 : 2010.08.30
  • 심사 : 2010.11.10
  • 발행 : 2010.11.25
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초록

본 논문은 고성능32비트 AES구조를 제시한다. 재배열 구조는 5단 파이프라인을 사용한다. 그 안에 ShiftRows/InvShiftRows 모듈은 4단 파이프라인을 사용하고 MixColumn/InvMixColumn 모듈은 1단 파이프라인을 사용한다. Shift rows와 inverse shift rows 같은 구조를 사용한다. Mix column 과 inverse mix column 도 같은 구조를 사용한다. 그리고 RCON구조를 단순화 하여 사이즈를 줄였다. 제안된 구조는 verilogHDL 을 이용하여 구현 하였다. 이 회로의 처리량은 415Mbits/s 이고 크기는 0.18um CMOS 공정에서 13,764 게이트 이다. 재배열 구조는 무선 네트워크 라우터에서 사용할 수 있다.

This paper presents a high performance 32-bit single core AES architecture. The proposed architecture employs a 5-stage pipeline: four stages in the ShiftRows/InvShiftRows module, and one stage in the MixColumn/InvMixColumn module. Circuit size reduction has been achieved through merging of the shift rows and inverse shift rows. The mix column and inverse mix column share the same resources. Three 32-bit registers replace the conventional ten 32-bit registers in the RCON architecture. The proposed architecture has been implemented in Verilog HDL, and yields 415 Mbits/s throughput with the circuit size of 13764 gate equivalents on the 0.18um CMOS process technology. This high performance architecture is suitable for wireless network router applications.

키워드

참고문헌

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